(IFETCH) output identifies the bus cycles in which the operand is loaded into the in-
struction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these
two signals allows a bus analyzer to synchronize itself to the instruction stream and
monitor its activity.
5.10.4 On-Chip Breakpoint Hardware
An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap
on any memory access. Off-chip address comparators preclude breakpoints unless
show cycles are enabled. Breakpoints on instruction prefetches that are ultimately
flushed from the instruction pipeline are not acknowledged; operand breakpoints are
always acknowledged. Acknowledged breakpoints initiate exception processing at the
address in exception vector number 12, or alternately enter background mode.
5.11 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the perfor-
mance of the CPU32, a loop mode has been added to the processor. The loop mode
is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction. Figure 5-12 shows the
required form of an instruction loop for the processor to enter loop mode.
5
ONE WORD INSTRUCTION
DBCC
DBCC DISPLACEMENT
$FFFC = – 4
1126A
Figure 5-12 Loop Mode Instruction Sequence
The loop mode is entered when the DBcc instruction is executed, and the loop dis-
placement is –4. Once in loop mode, the processor performs only the data cycles as-
sociated with the instruction and suppresses all instruction fetches. The termination
condition and count are checked after each execution of the data operations of the
looped instruction. The CPU32 automatically exits the loop mode on interrupts or other
exceptions. All single word instructions that do not cause a change of flow can be
looped.
MC68331
CENTRAL PROCESSING UNIT
MOTOROLA
5-25
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
