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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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Sources of external exception include interrupts, breakpoints, bus errors, and reset re-  
quests. Interrupts are peripheral device requests for processor action. Breakpoints are  
used to support development equipment. Bus error and reset are used for access con-  
trol and processor restart.  
5.9.3 Exception Processing Sequence  
For all exceptions other than a reset exception, exception processing occurs in the fol-  
lowing sequence. Refer to 4.6 Reset for details of reset processing.  
As exception processing begins, the processor makes an internal copy of the status  
register. After the copy is made, the processor state bits in the status register are  
changed — the S bit is set, establishing supervisor access level, and bits T1 and T0  
are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority  
mask is also updated.  
Next, the exception number is obtained. For interrupts, the number is fetched from  
CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions,  
internal logic provides a vector number.  
Next, current processor status is saved. An exception stack frame is created and  
placed on the supervisor stack. All stack frames contain copies of the status register  
and the program counter for use by RTE. The type of exception and the context in  
which the exception occurs determine what other information is stored in the stack  
frame.  
5
Finally, the processor prepares to resume normal execution of instructions. The ex-  
ception vector offset is determined by multiplying the vector number by four, and the  
offset is added to the contents of the VBR to determine displacement into the excep-  
tion vector table. The exception vector is loaded into the program counter. If no other  
exception is pending, the processor will resume normal execution at the new address  
in the PC.  
5.10 Development Support  
The following features have been implemented on the CPU32 to enhance the instru-  
mentation and development environment:  
• M68000 Family Development Support  
• Background Debugging Mode  
• Deterministic Opcode Tracking  
• Hardware Breakpoints  
5.10.1 M68000 Family Development Support  
All M68000 Family members include features to facilitate applications development.  
These features include the following:  
Trace on Instruction Execution — M68000 Family processors include an instruction-  
by-instruction tracing facility as an aid to program development. The MC68020,  
MC68030, MC68040, and CPU32 also allow tracing only of those instructions  
MC68331  
CENTRAL PROCESSING UNIT  
MOTOROLA  
5-17  
USER’S MANUAL