16
15
0
S/C
DATA FIELD
STATUS CONTROL BIT
Figure 5-10 BDM Serial Data Word
Table 5-6 CPU Generated Message Encoding
Bit 16
Data
xxxx
Message Type
Valid Data Transfer
0
0
1
1
1
FFFF
0000
0001
FFFF
Command Complete; Status OK
Not Ready with Response; Come Again
BERR Terminated Bus Cycle; Data Invalid
Illegal Command
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Motorola reserves the right to
use this bit for future enhancements.
5
5.10.2.8 Recommended BDM Connection
In order to provide for use of development tools when an MCU is installed in a system,
Motorola recommends that appropriate signal lines be routed to a male Berg connec-
tor or double-row header installed on the circuit board with the MCU, as shown in the
following figure.
DS
GND
1
3
5
7
9
2
4
6
8
BERR
BKPT/DSCLK
FREEZE
GND
RESET
IFETCH/DSI
V
DD
10 IPIPE/DSO
32 BERG
Figure 5-11 BDM Connector Pinout
5.10.3 Deterministic Opcode Tracking
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch
MOTOROLA
5-24
CENTRAL PROCESSING UNIT
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
