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MC33389CDW 参数 Datasheet PDF下载

MC33389CDW图片预览
型号: MC33389CDW
PDF下载: 下载PDF文件 查看货源
内容描述: 系统基础芯片,低速容错CAN [System Basis Chip with Low Speed Fault Tolerant CAN]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 35 页 / 592 K
品牌: MOTOROLA [ MOTOROLA ]
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FreesScPaI RlEeGISSTMeERCmS33Di3cE8S9oCRnIPdTuIOcNtor, Inc.  
This register is used to read back the overtemperature status for the V1 and V2 regulators. In write mode, it is used to turn V2  
on after a V2 over temperature shutdown has occurred.  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
OTV2  
OTV2C  
0
BIT 0  
OTV1  
R
OPWV2  
OPWV1  
OTSR  
$012  
W
RESET  
0
0
0
OTV1: 1=V1 overtemperature shutdown, 0=V1 no overtemperature  
OTV2: 1=V2 overtemperature shutdown, 0=V2 no overtemperature  
OPWV1: 1=V1 overtemperature pre-warning, 0=V1 normal temperature  
OPWV2: 1=V2 overtemperature pre-warning, 0=V2 normal temperature  
In case of V1 or V2 overtemperature the appropriate voltage regulators are switched off automatically and the  
overtemperature flags are set (latched). The flags can be reseted by a read operation of the register OTSR.  
Once V2 has been switched off because of overtemp (OTV2=1) it can only be switched on again by forcing OTV2C=0 by a  
write operation.  
The V1 and V2 pre-warning flags are set as long as the first overtemperature exists. The flags disappear, when the  
temperature is below the threshold. An overtemperature of the V2 power supply will also switch off V3. After a power on reset all  
bits of the register are set to 0.  
Table 46. TESRH — Transceiver Error Status Register For CANH  
Register used to report the CAN H failure status  
.
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
R
TESRH3  
TESRH2  
TESRH1  
TESRH0  
TESRH  
$014  
W
RESET  
0
0
0
0
Table 47.  
TESRH3  
TESRH2  
TESRH1  
TESRH0  
0
0
X
0
1
0
X
X
1
0
0
1
0
0
0
1
No failure on CANH  
CANH wire interruption  
CANH short circuited to Vbat  
CANH short circuited to ground  
CANH short circuited to VCC  
X
X
X
X
In case of CANH line failures, the appropriate bit(s) are set according to table 46. This information is latched. The register  
can be reseted by a read operation. After power on reset, all bits are set to 0.  
Table 48. TESRL — Transceiver Error Status Register For CANL And Tx  
Register used to report the CANL and Tx permanent dominant failure status  
.
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
R
TESRL3  
TESRL2  
TESRL1  
TESRL0  
TESRL  
$017  
W
RESET  
0
0
0
0
For More Information On This Product,  
MC33389  
MOTOROLA  
27  
Go to: www.freescale.com  
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