V58C2128(804/404/164)S
V 58 C 2 128(80/40/16) 4 S X T XX
SPEED
MOSEL VITELIC
MANUFACTURED
6 (166MHZ@CL2.5)
7 (143MHZ@CL2.5))
75(133MHZ@CL2.5)
8 (125MHZ@CL2.5)
DDRSDRAM
COMPONENT
PACKAGE, T = TSOP
CMOS
2.5V
COMPONENT
REV LEVEL
128Mb, 4K Refresh
x8, x4, x16
SSTL
4 Banks
Block Diagram
32M x 4
Row Addresses
Column Addresses
A0 - A9, A11, AP, BA0, BA1
A0 - A11, BA0, BA1
Row address
buffer
Column address
counter
Column address
buffer
Refresh Counter
Row decoder
Row decoder
Row decoder
Row decoder
Memory array
Bank 0
Memory array
Bank 1
Memory array
Bank 2
Memory array
Bank 3
4096 x 1024
x 8
4096 x 1024
x 8
4096 x 1024
x 8
4096 x 1024
x 8
Control logic & timing generator
Input buffer
Output buffer
DQ0-DQ3
CK, CK
DQS
DLL
Strobe
Gen.
Data Strobe
V58C2128(804/404/164)S Rev. 1.6 March 2002
3