V58C2128(804/404/164)S
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
V58C2128(804/404/164)S Rev. 1.6 March 2002
3
QFC
CAS
RAS
WE
DM
CK
CK
CS
CILETIV LESO M
V
MOSEL VITELIC
MANUFACTURED
58
C
2 128(80/40/16) 4
S
X T XX
SPEED
6 (166MHZ@CL2.5)
7 (143MHZ@CL2.5))
75(133MHZ@CL2.5)
8 (125MHZ@CL2.5)
COMPONENT
PACKAGE, T = TSOP
DDRSDRAM
CMOS
2.5V
128Mb, 4K Refresh
x8, x4, x16
4 Banks
SSTL
COMPONENT
REV LEVEL
Block Diagram
32M x 4
Column Addresses
A0 - A9, A11, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Bank 3
4096 x 1024
x8
4096 x 1024
x8
4096 x 1024
x8
4096 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
MOSEL [ MOSEL VITELIC, CORP ]
