V58C2128(804/404/164)S
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA (The DDR SDRAM should be
0
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A ~ A in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
0
11
cycles are required to meet t
spec. The mode register contents can be changed using the same com-
MRD
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A ~ A , addressing mode
0
2
uses A , CAS latency (read latency from column address) uses A ~ A . A is a Mosel Vitelic specific test
3
4
6
7
mode during production test. A is used for DLL reset. A must be set to low for normal MRS operation. Refer
8
7
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
Address Bus
BA1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
QFC I/O DLL
Extended Mode Register
Mode Register
0
0
MRS
MRS
RFU : Must be set "0"
RFU
DLL TM
BT Burst Length
CAS Latency
A
0
1
1
I/O Strength
Full
A
0
1
0
DLL Enable
Enable
A
0
1
3
Burst Type
Sequential
Interleave
A7
0
A
8
DLL Reset
No
mode
Normal
Test
0
Half
Disable
1
1
Yes
Burst Length
CAS Latency
Latency
BA
0
0
A
n
~ A
0
A
0
0
0
0
1
1
1
1
6
A
5
A
0
1
0
1
0
1
0
1
4
Latency
Reserve
Reserve
2
A
2
A
1
A
0
Sequential
Reserve
2
Interleave
Reserve
2
(Existing)MRS Cycle
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
Extended Funtions(EMRS)
A
0
1
2
QFC Control
Disable
Enable
4
4
3
8
8
Reserve
Reserve
2.5
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
Reserve
Mode Register Set
0
1
2
3
4
5
6
7
8
CK,CK
*1
Mode
Register Set
Precharge
All Banks
Any
Command
Command
*2
RP
tMRD
tCK
t
V58C2128(804/404/164)S Rev. 1.6 March 2002
7
MOSEL [ MOSEL VITELIC, CORP ]
