V58C2128(804/404/164)S
Mode Register Set Timing
Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from
memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These parameters are programmable and are determined by address bits A
0
—A
3
during the
Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or
stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.
CILETIV LESO M
T0
T1
t
CK
T2
T3
t
RP
T4
T5
t
MRD
T6
T7
T8
T9
CK, CK
Command
Pre- All
MRS/EMRS
ANY
Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.
If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command
to allow time for the DLL to lock onto the clock.
Burst Mode Operation
Burst Length and Sequence
Burst Length
2
xx1
x00
x01
4
x10
x11
000
001
010
011
8
100
101
110
111
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
2, 3, 0, 1
3, 0, 1, 2
0,1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
2, 3, 0, 1
3, 2, 1, 0
0,1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
1, 0
0, 1, 2, 3
1, 2, 3, 0
1, 0
0, 1, 2, 3
1, 0, 3, 2
Starting Length (A
2
, A
1
, A
0
)
xx0
Sequential Mode
0, 1
Interleave Mode
0, 1
V58C2128(804/404/164)S Rev. 1.6 March 2002
8
MOSEL [ MOSEL VITELIC, CORP ]
