MITSUBISHI MICROCOMPUTERS
3827 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Serial I/O1 control register
Address 001A16
Receive buffer register
OE
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
UART control register
SP detector
PE FE
Address 001B16
Clock control circuit
Serial I/O synchronous clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit shift register
Transmit buffer register
Transmit interrupt source selection bit
P45/TXD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O status register Address 001916
Address 001816
Data bus
Fig. 23 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=1
TBE=0
TBE=1
ST
TSC=1✽
SP
Serial output TXD
ST
D
0
D
1
D
0
D1
SP
✽
1 start bit
Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input RXD
D
0
D
1
ST
D
0
D1
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 24 Operation of UART serial I/O1 function
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MITSUBISHI [ Mitsubishi Group ]
