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M38270EFMXXXFS 参数 Datasheet PDF下载

M38270EFMXXXFS图片预览
型号: M38270EFMXXXFS
PDF下载: 下载PDF文件 查看货源
内容描述: 单片8位CMOS微机 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER]
分类和应用: 计算机
文件页数/大小: 70 页 / 1104 K
品牌: MITSUBISHI [ Mitsubishi Group ]
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MITSUBISHI MICROCOMPUTERS  
3827 Group  
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER  
(1) Clock Synchronous Serial I/O Mode  
SERIAL I/O  
Clock synchronous serial I/O1 can be selected by setting the  
mode selection bit of the serial I/O1 control register to “1”.  
For clock synchronous serial I/O1, the transmitter and the receiver  
must use the same clock. If an internal clock is used, transfer is  
started by a write signal to the transmit/receive buffer registers.  
Serial I/O1  
Serial I/O1 can be used as either clock synchronous or asynchro-  
nous (UART) serial I/O. A dedicated timer (baud rate generator) is  
also provided for baud rate generation.  
Data bus  
Serial I/O1 control register  
Address 001A16  
Address 001816  
Receive buffer register  
Receive buffer full flag (RBF)  
Receive shift register  
Receive interrupt request (RI)  
P44/RXD  
Shift clock  
Clock control circuit  
P46/SCLK  
Serial I/O1  
clock selection bit  
Frequency division ratio 1/(n+1)  
BRG count source selection bit  
f(XIN  
)
Baud rate generator  
Address 001C16  
1/4  
(f(XCIN) in low-speed mode)  
1/4  
Clock control circuit  
Falling-edge detector  
P47/SRDY1  
F/F  
Transmit shift register shift completion flag (TSC)  
Shift clock  
Transmit shift register  
Transmit buffer register  
Transmit interrupt source selection bit  
P45/TXD  
Transmit interrupt request (TI)  
Transmit buffer empty flag (TBE)  
Serial I/O1 status register  
Address 001916  
Address 001816  
Data bus  
Fig. 21 Block diagram of clock synchronous serial I/O1  
Transfer shift clock  
(1/2 to 1/2048 of the internal  
clock, or an external clock)  
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
D4  
D4  
D5  
D5  
D6  
D6  
D7  
D7  
Serial output TXD  
Serial input RXD  
Receive enable signal SRDY1  
Write signal to receive/transmit  
buffer register (address 001816)  
RBF = 1  
TSC = 1  
TBE = 0  
TBE = 1  
TSC = 0  
Overrun error (OE)  
detection  
Notes  
1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)  
or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the  
serial I/O1 control register.  
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is  
output continuously from the TXD pin.  
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .  
Fig. 22 Operation of clock synchronous serial I/O1 function  
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