Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(5) The _R__D___Y__ signal
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RDY is a signal that facilitates access to an external device that requires long access time. As shown in
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Figure 1.11.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state.
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If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table
1.11.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.11.3 shows an
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example in which the RD signal is prolonged by the RDY signal.
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The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
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chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all
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bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Table 1.11.4. Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
___
_____
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R/W signal, address bus, data bus, CS
Maintain status when RDY signal received
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ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
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Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
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Figure 1.11.3. Example of RD signal extended by RDY signal
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