Advance Information
Serial Data Interface Timing
The MT9300 provides ST-BUS and GCI interface
timing. The Serial Interface clock frequency, C4i, is
4.096 MHz. The input and output data rate of the ST-
Bus and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS
or GCI format. The MT9300 automatically detects
the presence of an input frame pulse and identifies it
as either ST-BUS or GCI. In ST-BUS format, every
second falling edge of the C4i clock marks a bit
boundary, and the data is clocked in on the rising
edge of C4i, three quarters of the way into the bit cell
(See Figure 9). In GCI format, every second falling
edge of the C4i clock marks the bit boundary, and
data is clocked in on the second falling edge of C4i,
half the way into the bit cell (see Figure 10).
Base
Addr +
Echo Canceller A
00h Control Reg A1
01h Control Reg 2
02h Status Reg
03h Reserved
04h Flat Delay Reg
05h Reserved
06h Decay Step Size Reg
07h Decay Step Number
08h Reserved
0Ah Reserved
0Ch Rin Peak Detect Reg
MT9300
Base
Addr +
Echo Canceller B
20h Control Reg B1
21h Control Reg 2
22h Status Reg
23h Reserved
24h Flat Delay Reg
25h Reserved
26h Decay Step Size Reg
27h Decay Step Number
28h Reserved
2Ah Reserved
2Ch Rin Peak Detect Reg
2Eh Sin Peak Detect Reg
30h Error Peak Detect Reg
32h Reserved
34h DTDT Reg
36h Reserved
38h NLPTHR
3Ah Step Size, MU
3Ch Reserved
3Eh Reserved
Memory Mapped Control and Status
registers
Internal memory and registers are memory mapped
into the address space of the HOST interface. The
internal dual ported memory is mapped into
segments on a “per channel” basis to monitor and
control each individual echo canceller and
associated PCM channels. For example, in
Normal
configuration,
echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the
internal address space from 0A0h to 0BFh and
interfaces to PCM channel #5 on all serial PCM I/O
streams.
0Eh Sin Peak Detect Reg
10h Error Peak Detect Reg
12h Reserved
14h DTDT Reg
16h Reserved
18h NLPTHR
1Ah Step Size, MU
1Ch Reserved
1Eh Reserved
Figure 7 - Memory Mapping of per channel
Control and Status Registers
As illustrated in Figure 7, the “per channel” registers
provide independent control and status bits for each
echo canceller. Figure 8 shows the memory map of
the control/status register blocks for all echo
cancellers.
125
µsec
F0i
ST-Bus
F0i
GCI interface
Rin/Sin
Rout/Sout
Channel 0
Channel 1
Channel 30
Channel 31
Note: Refer to Figures 9 and 10 for timing details
Figure 6 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams
9
MITEL [ MITEL NETWORKS CORPORATION ]
