MT9300
Advance Information
the rising edge of TCK pulses. This pin is
internally pulled to VDDwhen it is not driven from
an external source.
•
Test Data Output (TDO)
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or data register are serially
shifted out towards the TDO. The data from the
TDO is clocked on the falling edge of the TCK
pulses. When no data is shifted through the
Boundary Scan cells, the TDO driver is set to a
high impedance state.
•
Test Reset (TRST)
This pin is used to reset the JTAG scan
structure. This pin is internally pulled to VSS.
Instruction Register
In accordance with the IEEE 1149.1 standard, the
MT9300 uses public instructions. The JTAG Interface
contains a 3-bit instruction register. Instructions are
serially loaded into the instruction register from the
TDI when the TAP Controller is in its shifted-IR state.
Subsequently, the instructions are decoded to
achieve two basic functions: to select the test data
register that will operate while the instruction is
current, and to define the serial test data register
path, which is used to shift data between TDI and
TDO during data register scanning.
Test Data Registers
As specified in IEEE 1149.1, the MT9300 JTAG
Interface contains three test data registers:
•
Boundary-Scan register
The Boundary-Scan register consists of a
series of Boundary-Scan cells arranged to form
a scan path around the boundary of the
MT9300 core logic.
•
•
Bypass Register
The Bypass register is a single stage shift
register that provides a one-bit path from TDI
TDO.
Device Identification register
The Device Identification register provides
access to the following encoded information:
device version number, part number and
manufacturer's name.
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