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MT9092 参数 Datasheet PDF下载

MT9092图片预览
型号: MT9092
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 -CMOS ST- BUS⑩系列数字电话与HDLC ( HPhone - II ) [ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II)]
分类和应用: 电话
文件页数/大小: 42 页 / 484 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9092  
reference to review each of the control/status bit  
definitions without the need to locate them in the text  
of the functional block descriptions.  
Register Summary  
This section contains a complete listing of the  
HPhone-II register addresses, the control/status bit  
mapping associated with each register and a  
definition of the function of each control/status bit.  
The Register Summary may be used for future  
HDLC Address Recognition Register 1  
ADDRESS = 00h WRITE/READ VERIFY  
Power Reset Value  
0000 0000  
Adr16 Adr15 Adr14 Adr13 Adr12 Adr11 Adr10 A1EN  
7
6
5
4
3
2
1
0
Adr 16-11 A six bit mask used to interrogate the first byte of the received address. Adr16 is MSB. In the Q.921 specification these  
bits are defined to be Sapi5-0.  
Adr 10  
This bit is used in address comparison if a seven bit address is being checked for (Control bit Seven of Control Register 2  
is set). In the Q.921 specification this bit is defined to be C/R (Command/Response).  
A1EN  
When this bit is high, this six (or seven) bit mask is used in address comparison of the first address byte. If address  
recognition is enabled, any packet failing the address comparison will not be stored in the RX FIFO. A1EN must be high  
for All-call (1111111) address recognition for single byte address. When this bit is low, this bit mask is ignored in address  
comparison.  
HDLC Address Recognition Register 2  
ADDRESS = 01h WRITE/READ VERIFY  
Power Reset Value  
0000 0000  
Adr26 Adr25 Adr24 Adr23 Adr22 Adr21 Adr20 A2EN  
7
6
5
4
3
2
1
0
Adr 26-20 A seven bit mask used to interrogate the second byte of the received address. Adr26 is MSB. This mask is ignored (as well  
as first byte mask) if an All call address (1111111) is received. In the Q.921 specification these bits are defined to be  
Tei6-0.  
A2EN  
When this bit is high this seven bit mask is used in address comparison of the second address byte. If address recognition  
is enabled, any packet failing the address comparison will not be stored in the RX FIFO. A2EN must be high for All-call  
address recognition. When this bit is low, this bit mask is ignored in address comparison.  
HDLC Transmit/Receive FIFO Register  
ADDRESS = 02h WRITE/READ  
Power Reset Value  
Not Applicable  
D7  
7
D6  
6
D5  
5
D4  
4
D3  
3
D2  
2
D1  
1
D0  
0
The Transmitter FIFO is 19 words deep. Each word consists of 8 bits of data from the internal data bus and 2 status bits from CON-  
TROL Register 1 (EOP and FA). If there is data in the Tx FIFO then the lowest data byte in it is loaded into an output shift register for  
transmission, and the remaining data shifts down by one word position (Tx FIFO read). A write to a full Tx FIFO will update the top byte  
only.  
The receiver FIFO is 19 words deep. During a receiver write, the last 8 bits of a shift register buffer and two status bits are loaded into  
7-22  
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