MT9092
PWRST
IC
VRef
VBias
NC
M+
M-
VSSA
MIC+
MIC-
VSS SPKR
DSTi
DSTo
C4i
F0i
VSSD
IRQ
SCLK
DATA 2
DATA 1
CS
WD
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
BP
S12
S11
S10
S9
S8
Pin Description
Pin
#
1
2
3
4
5
6
7
8
Name
M+
NC
V
Bias
V
Ref
IC
Description
Non-Inverting Microphone (Input).
Non-inverting input to microphone amplifier from the
handset microphone.
No Connect.
No internal connection to this pin.
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1 µF capacitor to V
SSA
.
Reference voltage for codec (Output).
Nominally [(V
DD
/2)-1.5] volts. Used internally.
Connect 0.1 µF capacitor to V
SSA
.
Internal Connection.
Tie externally to V
SS
for normal operation.
PWRST
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
DSTi
DSTo
ST-BUS Serial Stream (Input).
2048 kbit/s input stream composed of 32 eight bit channels;
the first four of which are used by the MT9092. Input level is TTL compatible.
ST-BUS Serial Stream (Output).
2048 kbit/s output stream composed of 32 eight bit
channels. The MT9092 sources digital signals during the appropriate channel, time coincident
with the channels used for DSTi.
4096 kHz Clock (Input).
CMOS level compatible.
Frame Pulse (Input).
CMOS level compatible. This input is the frame synchronization pulse
for the 2048 kbit/s ST-BUS stream.
Digital Ground .
Nominally 0 volts.
Interrupt Request (Open Drain Output).
An active low output indicating an unmasked HDLC
interrupt event. Requires 1 kΩ pull-up to V
DD
.
Serial Port Synchronous Clock (Input).
Data clock for MCS-51 compatible microport. TTL
level compatible.
9
10
11
12
13
C4i
F0i
V
SSD
IRQ
SCLK
7-4
IC
NC
NC
VSSD
S1
S2
S3
S4
S5
S6
S7
44 PIN PLCC
18
19
20
21
22
23
24
25
26
27
28
Figure 2 - Pin Connections
MITEL [ MITEL NETWORKS CORPORATION ]
