MT9092
Transducer Interfaces
HSPKR+
Four standard telephony transducer interfaces are
provided by the HPhone-II. These are:
75 Ω
1000 pF
➧
The handset microphone inputs (transmitter),
pins M+/M- and the speakerphone microphone
inputs, pins MIC+/MIC-. The transmit path is
muted/not-muted by the MIC EN control bit.
Selection of which input pair is to be routed to
the transmit filter amplifier is acomplished by the
MIC/HNSTMIC control bit. Both of these reside
in the Transducer Control Register (address
0Eh). The nominal transmit path gain may be
adjusted to either 6.1dB (suggested for µ-Law)
or 15.4dB (suggested for A-Law). Control of this
gain is provided by the MICA/u control bit
(General Control Register, address 0Fh). This
gain adjustment is in addition to the
programmable gain provided by the transmit
filter and DSP.
150 ohm
load
(speaker)
MT9092
75 Ω
1000 pF
ground
HSPKR-
Figure 5- Handset Speaker Driver
LCD
A twelve segment, non-multiplexed, LCD display
controller is provided for easy implementation of
various set status and call progress indicators. The
➧
The handset speaker outputs (receiver), pins
HSPKR+/HSPKR-.
This
internally
compensated, fully differential output driver is
capable of driving the load shown in Figure 5.
This output is enabled/disabled by the HSSPKR
EN bit residing in the Transducer Control
Register (address 0Eh). The nominal handset
receive path gain may be adjusted to either
-12.3dB (suggested for µ-Law) or -9.7dB
(suggested for A-Law). Control of this gain is
provided by the RxA/u control bit (General
Control Register, address 0Fh). This gain
adjustment is in addition to the programmable
gain provided by the receive filter and DSP.
twelve output pins (S ) are used in conjunction with
n
12 segment control bits, located in LCD Segment
Enable Registers 1&2 (addresses 12h and 13h), and
the BackPlane output pin (BP) to control the on/off
state of each segment individually.
The BP pin drives a continuous 62.5Hz, 50% duty
cycle squarewave output signal. An individual
segment is controlled via the phase relationship of its
segment driver output pin with respect to the
backplane, or common, driver output. Each of the
twelve Segment Enable bits corresponds to a
segment output pin. The waveform at each segment
pin is in-phase with the BP waveform when its
control bit is set to logic zero (segment off) and is
out-of-phase with the BP waveform when its control
bit is set to a logic high (segment on). Refer to the
LCD Driver Characteristics for pin loading
information.
➧
The loudspeaker outputs, pins SPKR+/SPKR-.
This internally compensated, fully differential
output driver is capable of directly driving 6.5vpp
into a 40 ohm load. This output is enabled/
disabled by the SPKR EN bit residing in the
Transducer Control Register (address 0Eh). The
nominal gain for this amplifier is 0.2dB.
Microport
C-Channel
A serial microport, compatible with Intel MCS-51
(mode 0) specifications, provides access to all
HPhone-II internal read and write registers. This
microport consists of three pins; a half-duplex
transmit/receive data pin (DATA1), a chip select pin
(CS) and a synchronous data clock pin (SCLK).
Access to the internal control and status registers of
Mitel basic rate, layer 1, transceivers is through the
ST-BUS Control Channel (C-Channel), since direct
microport access is not usually provided, except in
the case of the SNIC (MT8930). The HPhone-II
provides asynchronous microport access to the ST-
BUS C-Channel information on both DSTo and DSTi
via a double-buffered read/write register (address
14h). Data written to this address is transmitted on
On power-up reset (PWRST) or with a software reset
(RST), the DATA1 pin becomes a bidirectional
(transmit/receive) serial port while the DATA2 pin is
internally disconnected and tri-stated.
the C-Channel every frame when enabled by CH EN
1
(see ST-BUS/Timing Control).
7-17
MITEL [ MITEL NETWORKS CORPORATION ]
