MT90810
Preliminary Information
Test Access Port (TAP)
JTAG Support
The Test Access Port (TAP) provides access to many
test support functions built into the FMIC. It consists
of three input connections and one output
connection. The following connections form the TAP:
The FMIC JTAG interface is designed to the
Boundary-Scan standard IEEE1149.1. The standard
specifies a design-for-testability technique called
Boundary-Scan Test (BST). A boundary-scan IC has
a shift-register stage or ‘Boundary-Scan Cell’ (BSC)
in between the core logic and the I/O buffers
adjacent to each I/O pin. The BSCs can control and
observe what happens at each I/O pin of the IC. The
operation of the boundary-scan circuitry is controlled
by a Test Access Port (TAP) Controller.
•
Test Clock Input (TCK)
TCK provides the clock for the test logic. The
TCK must not interfere with any on-chip clock
and thus remain independent. This permits
shifting of test data into or out of the Boundary-
Scan register cells concurrently with the
operation of the device without interfering with
on-chip logic.
BOUNDARY -SCAN CELL(BSC)
T
•
Test Mode Select Input (TMS)
BSC
BSC
TEST DATA IN (TDI)
TEST CLOCK (TCK)
BSC
BSC
A
P
The logic signal (0’s and 1’s) received at the
TMS input are interpreted by the TAP Controller
to control the test operations. The TMS signals
are sampled at the rising edge of the TCK
pulses. When TMS is not driven from an
external source, the test logic perceives a logic
1.
C
O
N
T
CORE LOGIC
TEST MODE
SELECT (TMS)
R
O
L
L
E
R
BSC
BSC
BSC
BSC
TEST DATA OUT (TDO)
Figure 12 - A Typical Boundary-Scan IC
I[0:1] Instruction
Description
[00] EXTEST
Boundary-Scan
This instruction is specifically provided to allow board-level interconnect
register selected, testing of opens, bridging errors etc.
Test Enabled
When the EXTEST instruction is selected, the on-chip logic is isolated
from the FMIC’s I/O pin such that the value of the I/O pins is determined
by its boundary-scan register. Data for the execution of this instruction
can be preloaded into the boundary-scan register with the SAMPLE/
PRELOAD instruction.
[01] SAMPLE/
PRELOAD
Boundary-Scan
Two functions can be performed by the use of this instruction. It allows a
register selected, SAMPLE (‘snapshot’) of the normal operation of the FMIC to be taken for
Test Disabled
examination. And, prior to the selection of another test operation, a
PRELOAD can place data values into the latched parallel outputs of the
Boundary-Scan cells. During the execution of the instruction, the on-chip
logic operation is not hampered in any way.
[10] BYPASS/
TEST
Bypass register
selected,
Test Enabled
This instruction is used to BYPASS the FMIC while sampling or loading
the data registers in other devices with scan registers in the same serial
register chain. The FMIC is in test mode and the value of it’s I/O pins is
determined by its boundary-scan register.
[11] BYPASS/
NOTEST
Bypass register
selected,
Test Disabled
This instruction is used to BYPASS the FMIC while performing boundary-
scan testing on other devices with scan registers in the same serial
register chain. The FMIC is allowed to function normally. This instruction
is automatically loaded upon reset of the FMIC, as specified in
IEEE1149.1
Table 23 - Instruction Register
2-166
MITEL [ MITEL NETWORKS CORPORATION ]
