Preliminary Information
MT90810
Bit
7-4
3
Name
Description
RESERVED
CSTo
CSTo. The inverted value of this bit is output on the CSTo pin and is available for
general purpose system timing functions. The CSTo bit for each of the local output
channels is multiplexed onto the CSTo pin as illustrated below:
F0
C4
CSTo output timing
LD0:0 LD1:0 LD2:0 LD3:0 LD0:1 LD1:1 LD2:1 LD3:1 LD0:2 LD1:2 LD2:2 LD3:2 LD0:3
2
MC
Message Channel. This bit, when set, will send the eight bits of connection memory
low directly out the corresponding output channel and stream. When the bit is cleared,
the contents of the programmed location in connection memory low act as an address
for the data memory and so determine the source of the corresponding output channels
and stream.
1
0
CE
Channel Enable. If the DMA_EN bit in the Control/Status register is set, then this bit
flags the control logic to perform a bidirectional DMA transfer for this input/output
channel pair. When the bit is clear, the DMA transfer for this channel pair is disabled.
If DMA operations are not enabled then this bit must be cleared.
CAB8
Source Channel Address Bit 8. This bit, together with bits CAB0-7 in connection
memory low, is used to select one of 384 different source input channels for the
connection.
Table 22 - Connection Memory High Bits for Local channels
2-165
MITEL [ MITEL NETWORKS CORPORATION ]
