Preliminary Information
MT90810
•
The Test Data Input (TDI)
The FMIC boundary-scan register contains 84 bits.
Bit 0 in Table 24 - “Boundary Scan Register” is the
first bit clocked out. All tristate enable bits are
Serial input data applied to this port is fed either
into the instruction register or into a test data
register, depending on the sequence previously
applied to the TMS input. Both registers are
described in a subsequent section. The
received input data is sampled at the rising
edge of the TCK pulses. When TDI is not driven
from an external source, the test logic
perceives a logic 1.
asserted high i.e.,
a
logic
1
enables the
corresponding group of outputs/bidirectionals. Note
that clocking all zeros into the scan path register will
set all outputs to tristate.
Bits
Definition
•
The Test Data Output (TDO)
0:11
FGB[11:0]
FGA[11:0]
DSo[7:0]
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or a data register are
serially shifted out towards the TDO. The data
out of the TDO is clocked at the falling edge of
the TCK pulses. When no data is shifted
through the cells, the TDO driver is set to an
inactive state.
12:23
24:31
32
tristate enable for DSo[7:0]
DSi[7:0]
33:40
41
tristate enable for DSi[7:0]
F0 , C4 , C2 , SEC8K
tristate enable for
42:45
46
Instruction Register
In accordance with the IEEE 1149.1 standard, the
FMIC uses public instructions listed in Table 23 -
“Instruction Register” . The FMIC JTAG Interface
contains a two bit instruction register. Instructions
are serially loaded into the Instruction Register from
the TDI when the TAP Controller is in its Shift-IR
state. Subsequently, the instructions are decoded to
achieve two basic functions: to select the test data
register that may operate while the instruction is
current and to define the serial test data register path
that is used to shift data between TDI and TDO
during data register scanning.
47:51
52
FRAME, CLK8, CLK4, CLK2, CSTo
tristate enable for ALL output only pins
EX8KA, EX8KB
53:54
55:58
59:62
63:70
71
LDO[3:0]
LDI[3:0]
D[7:0]
tristate enable for D[7:0]
RDY, ERR, DREQ[1:0]
72:75
76:83
RD, WR, CS, ALE, A[1:0], DACK[1:0]
Test Data Registers
Table 24 - Boundary Scan Register
As specified in the IEEE 1149.1 Standard, the FMIC
JTAG interface contains two test data registers:
•
The Boundary Scan Register
The Boundary-Scan Register consists of a
series of Boundary-Scan Cells arranged to form
a scan path around the boundary of the core
logic of the FMIC.
•
The Bypass Register
The Bypass Register is a single stage shift-
register that provides a one-bit path that
minimizes the distance for test data shifting
from the FMIC’s TDI to its TDO.
2-167
MITEL [ MITEL NETWORKS CORPORATION ]
