MT90810
Preliminary Information
t
FW
t
FRAME
CLK 8
t
FS
FH
t
C8P
t
t
C8L
C8H
t
C4P
CLK 4
CLK 2
t
t
C4L
C4H
t
C2P
t
C2L
t
C2H
(2 MHz
t
PD
Bit Rate)
LDO
LDI
t
S
t
(4 MHz
Bit Rate)
H
t
PD
t
PD
LDO
LDI
t
S
t
H
(8 MHz
Bit Rate)
t
PD
LDO
LDI
t
S
t
H
Note: *Timing for CLK is shown for LOC_CLK register set to 00hex
Figure 14 - Local Stream Timing
16 MHz Clock
(FMIC Internal Signal)
t
PD
FGA [0:11]
FGB [0:11]
Figure 15 - Local Frame Timing
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