MT90810
Preliminary Information
Bit
Name
Description
Frame Start (FRMx_STRT) Register x
7:0 STRT(7:0)
Lower 8 bits of the 11 bit quantity specified in Table 13 - “Frame Group
Mode bits”
Frame Mode (FRMx_STRT) Register x
7:6
MODE
Frame Group Mode
2 [10] Normal Framing
3 [11] Inverted Framing
5
FRM_TYPE
BIT_RATE
Type of framing signal for this group
0 Frame pulse is one bit cell wide
1 Frame pulse is eight bit cell wide
4:3
Frame Group bit rate register
Spacing for the framing pulses is for:
0 [00] 2Mb/s data rate
1 [01] 4Mb/s data rate
2 [10] 8Mb/s data rate
3 [11] Reserved
2:0
STRT(11:8)
Upper three bits of the 11 bit quantity specified in Table 13 - “Frame Group
Mode bits”
Table 16 - Frame Register bits for modes 2&3
Bit
Name
Description
7:3
2
RESERVED
VCO_BYP
Should NEVER be set under normal operating conditions
Bypass On-chip VCO
External VCO may be used in place of FMIC VCO
1
0
RESERVED
SEL_XIN
Should NEVER be set under normal operating conditions
Select X1 as chip master clock, direct input to FMIC state machine.
Bypass entire On-chip APLL (including VCO)
Table 17 - Diagnostic (DIAG_REG) Register
2-162
MITEL [ MITEL NETWORKS CORPORATION ]
