Preliminary Information
MT90810
Mode [bits]
Description
FGx[0:11] are programmable output pins. All 8 bits of FRMx_START register are driven
0 [00]
Programmed output
1
out pins FGx[0:7] (with bit 0 corresponding to pin FGx[0] etc.) and bits 0-3 of
FRMx_MODE register are driven out pin FGx[8:11] (with bit 0 corresponding to pin
FGx[8] etc.).
1 [01]
DSi/DSo output enables
FGA[4:11] pins correspond to output drive enables for the MVIP DSo streams 0 to 7,
respectively.
FGB[4:11] pins correspond to output drive enables for the MVIP DSi streams 0 to 7,
respectively.
FGx[0:3] are programmable output pins. The least significant four bits of FRMx_MODE
register are driven out pins FGx[0:3] (with bit 0 corresponding to pin FGx[0] etc.).
2 [10]
3 [11]
Normal Framing
Frame groups A&B (FGx[0:11]) are programmed as output framing pulses for use with
the local serial data streams (see Figure 19 - “Frame Pulse Timing for Mode 2” ). The
position of the first framing signal in a group is determined by an 11 bit quantity. The
quantity is the FMIC state number minus one. The quantity determines when the first
framing signal in a group is to be asserted high.
Inverted Framing
Identical to Normal Framing except the polarity of the framing pulses is logically inverted.
Table 13 - Frame Group Mode bits
1. FRMx represents either FRMA for frame group A, or FRMB for group B.
Bit
Frame Start (FRMx_STRT) Register x
7:0 PROG_OUT(7:0) All 8 bits are driven out FGx[7:0]
Frame Mode (FRMx_MODE) Register x
Name
Description
7:6
MODE
Frame Group Mode
0 [00] Programmed Output
5:4
3:0
RESERVED
PROG_OUT(11:8)
All 4 bits are driven out FGx[11:8]
Table 14 - Frame Register bits for mode 0
Bit
Name
Description
Frame Start (FRMx_STRT) Register x
7:0 RESERVED
Frame Mode (FRMx_MODE) Register x
7:6
MODE
Frame Group Mode
1 [01] DSi/DSo output enable
5:4
3:0
RESERVED
PROG_OUT(3:0)
All 4 bits are driven out FGx[3:0]
Table 15 - Frame Register bits for mode 1
2-161
MITEL [ MITEL NETWORKS CORPORATION ]
