Preliminary Information
MT90810
Bit
Name
Bit Function
7
6
5
4
3
2
1
0
DACK1
DACK0
EX8KB
EX8KA
Read-only, reads logic value on DACK1 pin
Read-only, reads logic value on DACK0 pin
Read-only, reads logic value on EX8KB pin
Read-only, reads logic value on EX8KA pin
When set, inverts 8.192MHz CLK8 output pin
When set, inverts 4.096MHz CLK4 output pin
When set, inverts 2.048MHz CLK2 output pin
INV_CLK8
INV_CLK4
INV_CLK2
INV_FRM
When set, inverts FRAME output signal
Table 11 - Local Clock Control (LOC_CLK) Register
RESERVED
SER_CNFG
7
6
5
4
3
2
1
0
Figure 7 - Serial Mode (SER_MODE) Register
Mode
[bits]
Multiplexing of streams onto pins
LDI/O[str] where str=stream (0-3)
Description
0 [00]
2MHz streams
All local streams are configured to run at 2MHz.
Each channel occupies a 2Mb/s timeslot of 3.9µs.
LDI/O[0] = local stream 0
LDI/O[1] = local stream 1
LDI/O[2] = local stream 2
LDI/O[3] = local stream 3
2MHz,
32 channels
1 [01]
4MHz streams
LDI/O[0]
LDI/O[2]
local streams 0&1 are multiplexed onto pin LDI/O[0]
local streams 2&3 are multiplexed onto pin LDI/O[2]
Each channel occupies a 4Mb/s timeslot of 1.95µs.
(4MHz, 64
channels)
(4MHz, 64
channels)
channel 0
channel 1
channel 2
channel 3
etc....
stream0, ch0
stream1, ch0
stream0, ch1
stream1, ch1
stream2, ch0
stream3, ch0
stream2, ch1
stream3, ch1
2 [10]
8MHz streams
LDI/O[0]
all four local streams are multiplexed onto pins LDI/
O[0]
(8MHz, 128
channels)
Each channel occupies a 8Mb/s timeslot of 0.975µs.
channel 0
channel 1
channel 2
channel 3
channel 4
etc....
stream0, ch0
stream1, ch0
stream2, ch0
stream3, ch0
stream0, ch1
Table 12 - SER_CNFG bits (control configuration of local serial streams)
2-159
MITEL [ MITEL NETWORKS CORPORATION ]
