MT90810
Preliminary Information
Description
Mode
[bits]
APLL source
Frame Sync.
Function
0 [000] X1 divided by
1,2, or 4
no frame
sync.
FMIC as Timing Master
• FMIC defaults to this mode after reset (Clock Control Register
is cleared).
• X1 divided by 1,2 or 4 is used as the input to the APLL.
• State machine is free running and does not synchronize to any
external 8kHz source.
• XCLK_SEL can be programmed to any mode.
• MVIP_MST bit in MCS is set.
• Used when the FMIC is to become the timing master in a
system which has no digital network connections (T1 or E1).
1 [001] SEC8K >DPLL
2 [010] EX8KA >DPLL
3 [011] EX8KB >DPLL
no frame
sync.
FMIC as MVIP Master (Slaved to external 8kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
• State machine is not synchronized to external 8kHz (SEC8K/
EX8KA/B); that is, FRAME signal is freq locked but not
necessarily phase aligned with external 8kHz.
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS is set.
4 [100] MVIP C4
frame sync.
to F0
FMIC as MVIP Slave
• FMIC is entirely slaved to MVIP bus timing.
• MVIP C4 is selected as input to APLL.
• State machine is synchronized to MVIP C4 and F0 inputs.
• MVIP_MST bit in MCS register must be cleared.
5 [101] SEC8K >DPLL
6 [110] EX8KA >DPLL
frame sync.
to SEC8K
FMIC as MVIP Master (Slaved to external 8kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
• State machine is synchronized to external 8kHz (SEC8K/
EX8KA/B); that is, FRAME signal is freq locked and phase
aligned with external 8kHz.
frame sync.
to EX8KA
7 [111]
EX8KB >DPLL
frame sync.
to EX_8KB
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS must be set.
Table 9 - PLL_MODE bits (control PLL and frame synchronization)
Description
Mode [bits]
X1 =
Comments
0 [00]
1 [01]
2 [10]
3 [11]
16.384MHz
8.192MHz
4.096MHz
RESERVED
X1 must be 16.384MHz when PLL is in modes 1-3 or 5-7
Table 10 - XCLK_SEL bits (control divide ratio of X1 clock)
2-158