Preliminary Information
MT90810
Bits
Bit Function
7:0
All bits are written into the indirect address location specified by the LAR and AMR registers.
If auto increment on write/read is enabled, and connection memory is selected, then consecutive
writes/reads to/from the IDR will toggle between selection of high byte and low byte connection
memory.
Table 6 - Indirect Data Register [11]
Indirect Address
Name
CLK_CNTRL
Function
0
Clock Control Register
1
LOC_CLK
Local Output Clock Control
Local Serial Configuration Register
RESERVED
2
SER_MODE
3
4
5
FRMA_STRT
FRMA_MODE
FRMB_STRT
FRMB_MODE
Frame Group A start register
Frame Group A mode register
Frame Group B start register
Frame Group B mode register
RESERVED
6
7
8:11
12
DIAG_REG
RESERVED
Chip diagnostic bits
13:511
Table 7 - FMIC Control Register (read/write)
EN_SEC8K
SEL_S8K
PLL_MODE XCLK_SEL
7
6
5
4
3
2
1
0
Figure 6 - Clock Control (CLK_CNTRL) Register
Description
Name
Mode [bits]
Function
SEL_S8K
Selects source of 8kHz signal driven out on SEC8K pin
0 [00]
1 [01]
2 [10]
3 [11]
Select EX_8KA as SEC8K output
Select EX_8KB as SEC8K output
Select FRAME as SEC8K output
RESERVED
EN_SEC8K
Enables SEC8K as output
Table 8 - EN_SEC8K and SEL_S8K bits
2-157
MITEL [ MITEL NETWORKS CORPORATION ]
