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MT9079 参数 Datasheet PDF下载

MT9079图片预览
型号: MT9079
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS ST- BUS⑩系列高级控制器E1 [CMOS ST-BUS? FAMILY Advanced Controller for E1]
分类和应用: 控制器
文件页数/大小: 54 页 / 569 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9079  
8) When CRC-4 multiframing has been achieved,  
the primary basic frame alignment and resulting  
multiframe alignment will be adjusted to the basic  
b) Remote loopback (RxA and RxB to TxA and TxB  
respectively at the PCM 30 side). Bit RLBK = 0  
normal; RLBK = 1 activate.  
frame alignment  
determined during CRC-4  
synchronization. Therefore, the primary basic frame  
alignment will not be updated during the CRC-4  
multiframing search, but will be updated when the  
CRC-4 multiframing search is complete.  
MT9079  
Tx  
System  
PCM30  
DSTo  
Rx  
Channel Signalling  
c) ST-BUS loopback (DSTi to DSTo at the system  
side). Bit SLBK = 0 normal; SLBK = 1 activate.  
When control bit TxCAS is low the MT9079 is in  
Channel Associated Signalling mode (CAS); when  
TxCAS is high it is in Common Channel Signalling  
(CCS) mode. The CAS mode ABCD signalling  
nibbles can be passed either via the micro-ports  
(RPSIG = 1) or through related channels of the  
CSTo1 and CSTi2 serial links (RPSIG = 0), see  
Figure 4. Memory page five contains the receive  
ABCD nibbles and page six the transmit ABCD  
nibbles for micro-port CAS access.  
MT9079  
Tx  
DSTi  
System  
PCM30  
DSTo  
d) Payload loopback (RxA and RxB to TxA and TxB  
respectively at the system side with FAS and NFAS  
operating normally). Bit PLBK = 0 normal; PLBK = 1  
activate. The payload loopback is effectively a  
physical connection of DSTo to DSTi within the  
MT9079. Channel zero and the DL originate at the  
point of loopback.  
In CAS operation an ABCD signalling bit debounce  
of 14 msec. can be selected (DBNCE = 1). This is  
consistent with the signalling recognition time of  
CCITT Q.422. It should be noted that there may be  
as much as 2 msec. added to this duration because  
signalling equipment state changes are not  
synchronous with the PCM 30 multiframe.  
MT9079  
DSTi  
Tx  
If basic frame synchronization is lost (page 3,  
address 10H, SYNC = 1) all receive CAS signalling  
nibbles are frozen. Receive CAS nibbles will become  
unfrozen when basic frame synchronization is  
acquired.  
System  
Rx PCM30  
DSTo  
e) Local and remote time slot loopback. Remote  
time slot loopback control bit RTSL = 0 normal; RTSL  
= 1 activate, will loop around transmit ST-BUS time  
slots to the DSTo stream. Local time slot loopback  
bits LTSL = 0 normal; LTSL = 1 activate, will loop  
around receive PCM 30 time slots towards the  
remote PCM 30 end.  
When the SIGI interrupt is unmasked, IRQ will  
become active when a signalling nibble state change  
is detected in any of the 30 receive channels. The  
SIGI interrupt mask is located on page 1, address  
1CH, bit 0; and the SIGI interrupt vector (page 4,  
address 12H) is 01H.  
MT9079  
Loopbacks  
Tx  
DSTi  
System  
PCM30  
In order to meet PRI Layer 1 requirements and to  
assist in circuit fault sectionalization the MT9079 has  
six loopback functions. These are as follows:  
DSTo  
Rx  
The digital, remote, ST-BUS and payload loopbacks  
are located on page 1, address 15H, control bits 3 to  
0. The remote and local time slot loopbacks are  
controlled through control bits 4 and 5 of the per time  
slot control words, pages 7 and 8.  
a) Digital loopback (DSTi to DSTo at the PCM 30  
side). Bit DLBK = 0 normal; DLBK = 1 activate.  
MT9079  
DSTi  
Tx  
System  
PCM30  
DSTo  
4-251  
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