Preliminary Information
MT9076
Bit
Name
Functional Description
7
HDLC0I HDLC0 Interrupt. Whenever an unmasked HDLC0 interrupt occurs, this bit goes high.
Reading this register clears this bit.
6
5
4
HDLC1I HDLC1 Interrupt. Whenever an unmasked HDLC1 interrupt occurs, this bit goes high.
Reading this register clears this bit.
HDLC2I HDLC2 Interrupt. Whenever an unmasked HDLC2 interrupt occurs, this bit goes high.
Reading this register clears this bit.
JAI
Jitter Attenuator Error Interrupt. Whenever an unmasked JAI interrupt occurs.
If jitter attenuator FIFO comes within four bytes of an overflow or underflow, this bit goes
high. Reading this register clears this bit.
3
1SECI
One Second Status Interrupt. When unmasked this interrupt bit goes high whenever the
1SEC status bit (page 3 address 12H bit 7) goes from low to high. Reading this register
clears this bit.
2
1
0
5SECI
RCRI
SIGI
Five Second Status Interrupt. When unmasked this interrupt bit goes high whenever the 5
SEC status bit goes from low to high. Reading this register clears this bit.
RCRI Interrupt. Whenever an unmasked RCRI interrupt occurs. If remote alarm and CRC
error occur this bit goes high. Reading this register clears this bit.
signaling Interrupt. When unmasked this interrupt bit goes high whenever a change of
state (optionally debounced - see DBEn in the Data Link, signaling Control Word) is
detected in the signaling bits (AB or ABCD) pattern. Reading this register clears this bit.
Table 147 - Interrupt Word Three
(Page 4, Address 1EH) (E1)
Bit
Name
FERROL
Functional Description
7
6
5
Errored Frame Alignment Signal Counter Overflow Latch. This bit is set when
the errored frame alignment signal counter overflows. It is cleared after being read.
CRCOL
CRC Error Counter Overflow Latch. This bit is set when the crc error counter
overflows. It is cleared after being read.
FEBEOL
E bit Counter Overflow Latch. This bit is set when E bit counter overflows. It is
cleared after being read.
4
3
- - -
LCVOL
Line Code Violation Counter Overflow Latch. This bit is set when the line code
violation counter overflows. It is cleared after being read.
2
1
PRBSOL
Pseudo Random Bit Sequence Error Counter Overflow Latch. This bit is set
when the PRBS error counter overflows. It is cleared after being read.
PRBSMFOL
Pseudo Random Bit Sequence Multiframe Counter Overflow Latch. This bit is
set when the multiframe counter attached to the PRBS error counter overflows. It is
cleared after being read
0
- - -
Unused.
Table 148 - Overflow Reporting Latch
(Page 4, Address 1FH) (E1)
123
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