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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT9074  
Bit Name  
Functional Description  
Bit  
Name  
Functional Description  
7 - 0 PS7-0 This counter is incremented for each  
PRBS error detected on any of the  
receive channels connected to the  
PRBS error detector.  
7
D4YALML D4 Yellow Alarm Latch. This bit is  
set if a D4 yellow alarm is detected  
within a 600 millisecond integration  
period. It is cleared after a read.  
Table 56 - PRBS Error Counter  
(Page 4, Address 10H) (T1)  
6
5
D4Y48L D4  
Yellow  
Alarm  
(48  
milliseconds) Latch. This bit is  
set if a D4 yellow alarm is detected  
within a 48 millisecond integration  
period. It is cleared after a read.  
Bit  
Name  
Functional Description  
SECYELL Secondary D4 Yellow Alarm  
Latch. This bit is set if an alternate  
D4 (S bit in 12 th frame) is  
detected. It is cleared after a read.  
7 - 0 PSM7-0 This counter is incremented for each  
received CRC multiframe. It is  
cleared when the PRBS Error  
Counter is written to.  
4
3
2
ESFYELL ESF Yellow Alarm Latch. This bit  
is set upon receipt of a ESF yellow  
alarm. It is cleared after a read.  
Table 57 - CRC Multiframe Counter for PRBS  
(Page 4, Address 11H) (T1)  
BLUEL Blue Alarm Latch. This bit is set  
upon receipt of a blue alarm. It is  
cleared after a read.  
PDVL  
Pulse Density Violation Latch.  
This bit is set upon receipt of a  
pulse density violation. It is cleared  
after a read.  
1
0
LLEDL Line Loopback Enable Detect  
Latch. This bit is set upon receipt  
of a line loopback enable code. It is  
cleared after a read.  
LLDDL Line Loopback Disable Detect  
Latch. This bit is set upon receipt  
of a line loopback disable code. It  
is cleared after a read.  
Table 58 - Alarm Reporting Latch  
(Page 4, Address 12H) (T1)  
Bit  
Name  
Functional Description  
7 - 0 FC7 - 0 Framing Bit Counter. This eight bit  
counter will be incremented for each  
error in the received framing pattern.  
In ESF mode the ESF framing bits  
are monitored. In D4 mode Fs bits  
may be monitored as well as Ft bits.  
See - Section 15.5 Framing Bit  
Counter. The count is only active if  
the MT9074 is in synchronization.  
Table 59 - Framing Bit Counter  
(Page 4, Address 13H) (T1)  
59  
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