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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT9074  
Advance Information  
Bit  
Name  
Functional Description  
Bit  
Name  
Functional Description  
1
PRBSMFO Psuedo  
Random  
Bit  
7
FEO  
Framing Bit Error Counter  
Overflow Interrupt. When  
unmasked this interrupt bit  
goes high whenever the  
framing bit error counter  
changes from FFH to 00H.  
Reading this register clears this  
bit.  
Sequence  
Multiframe  
Counter Overflow Interrupt.  
When unmasked this interrupt  
bit goes high whenever the  
multiframe counter attached to  
the PRBS error counter  
overflows. FFH to 00H. 1 -  
unmasked, 0 - masked.  
6
5
CRCO  
OOFO  
CRC-6  
Error  
Counter  
0
MFOOFO  
Multiframes Out Of Sync  
Overflow Interrupt. When  
unmasked this interrupt bit  
goes high whenever the  
multiframes out of frame  
counter changes from FFH to  
00H. Reading this register  
clears this bit.  
Overflow Interrupt. When  
unmasked this interrupt bit  
goes high whenever the CRC-6  
error counter changes from  
FFH to 00H. Reading this  
register clears this bit.  
Out Of Frame Counter  
Overflow Interrupt. When  
unmasked this interrupt bit  
goes high whenever the out of  
frame counter changes state  
from changes from FFH to  
00H. Reading this register  
clears this bit.  
Table 68 - Interrupt Word Two  
(Page 4, Address 1DH) (T1)  
4
COFAO  
Change of Frame Alignment  
Counter Overflow Interrupt.  
When unmasked this interrupt  
bit goes high whenever the  
change of frame alignment  
counter changes from FFH to  
00H. Reading this register  
clears this bit.  
3
2
BPVO  
Bipolar Violation Counter  
Overflow Interrupt. When  
unmasked this interrupt bit  
goes high whenever the bipolar  
violation counter changes from  
FFH to 00H. Reading this  
register clears this bit.  
PRBSO  
Psuedo  
Random  
Bit  
Sequence Error Counter  
Overflow Interrupt. When  
unmasked this interrupt bit  
goes high whenever the PRBS  
error counter changes from  
FFH to 00H. Reading this  
register clears this bit.  
Table 68 - Interrupt Word Two  
(Page 4, Address 1DH) (T1)  
62  
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