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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT9074  
Bit  
Name  
Functional Description  
Bit Name  
Functional Description  
7
TFSYNI Terminal Frame Synchronization  
Interrupt. When unmasked this  
interrupt bit goes high whenever a  
change of state of terminal frame  
synchronization condition exists.  
Reading this register clears this bit.  
7
FEI Framing Bit Error Interrupt. When  
unmasked this interrupt bit goes high  
whenever an erroneous framing bit is  
detected (provided the circuit is in  
terminal frame sync). Reading this  
register clears this bit.  
6
MFSYNI Multiframe  
Synchronization  
6
5
4
CRCI CRC-6  
Error  
Interrupt.  
When  
Interrupt. When unmasked this  
interrupt bit goes high whenever a  
change of state of multiframe  
synchronization condition exists.  
Reading this register clears this bit.  
unmasked this interrupt bit goes high  
whenever a local CRC-6 error occurs.  
Reading this register clears this bit.  
YELI Yellow Alarm Interrupt. When  
unmasked this interrupt bit goes high  
upon detection of a yellow alarm.  
Reading this register clears this bit.  
5
4
- - -  
Unused.  
AISI  
Alarm Indication Signal Interrupt.  
When unmasked this interrupt bit  
goes high whenever a change of  
state of received all ones condition  
exists. Reading this register clears  
this bit.  
COFAI Change  
of  
Frame  
Alignment  
Interrupt. When unmasked this  
interrupt bit goes high whenever a  
change of frame alignment occurs  
after a reframe. Reading this register  
clears this bit.  
3
LOSI  
Loss of Signal Interrupt. When  
unmasked this interrupt bit goes  
high whenever a change of state of  
loss of signal (either analog - signal  
40 dB below nominal or digital - 192  
consecutive 0’s received) condition  
exists. Reading this register clears  
this bit.  
3
2
1
BPVI Bipolar Violation Interrupt. When  
unmasked this interrupt bit goes high  
whenever  
(excluding  
encountered. Reading this register  
clears this bit.  
a
bipolar  
violation  
is  
B8ZS encoding)  
PRBSI Psuedo Random Bit Sequence  
Error Interrupt. When unmasked this  
interrupt bit goes high upon detection  
of an error with a channel selected for  
PRBS testing. Reading this register  
clears this bit.  
2
1
0
SEI  
Severely Errored Frame Interrupt.  
When unmasked this interrupt bit  
goes high whenever a sequence of  
2 framing errors out of 6 occurs.  
Reading this register clears this bit.  
TxSLPI Transmit SLIP Interrupt. When  
unmasked this interrupt goes high  
whenever a controlled frame slip  
occurs in the transmit elastic buffer.  
Reading this register clears this bit.  
PDVI Pulse Density Violation Interrupt.  
When unmasked this interrupt bit goes  
high whenever in the absence of B8ZS  
coding a sequence of 16 consecutive  
zeros is received on the line, or the  
incoming pulse density is less than N  
ones in a time frame of 8(N+1) where  
N = 1 to 23. In the case of B8ZS  
coding, the interrupt is set upon  
detection of 8 consecutive zeros.  
Reading this register clears this bit.  
RxSLPI Receive SLIP Interrupt. When  
unmasked this interrupt bit goes  
high whenever a controlled frame  
slip occurs in the receive elastic  
buffer. Reading this register clears  
this bit.  
0
- - - Unused.  
Table 66 - Interrupt Word Zero  
(Page 4, Address 1BH) (T1)  
Table 67 - Interrupt Word One  
(Page 4, Address 1CH) (T1)  
61  
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