Advance Information
MT9074
Bit Name
Functional Description
Bit
Name
Functional Description
7 - 3 PD4 - Peak Detector Voltage Levels.
PD0 These five bits indicate the level of the
received signal AMI pulses.
7 - 3 TxTS4 - 0 Transmit Time Slot. A five bit
counter that indicates the number
of STBUS time slots between the
transmit elastic buffer STBUS write
frame boundary and the internal
transmit read frame boundary. The
count is updated every 250 uS.
PD4 PD3 PD2 PD1 PD0
Line Attenuation
less than 4dB
3-8dB
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
8-14dB
14-20dB
more than 20dB
2 - 0 TxBC2 - 0 Transmit Bit Count. A three bit
counter indicating the number of
STBUS bit times there are between
the transmit elastic buffer STBUS
write frame boundary and the
internal read frame boundary. The
count is updated every 250 uS.
2
LLOS LIU Loss of Signal indication. This
bit will be high when the received
signal is less than 40 dB below the
nominal value for a period of at least 1
msec. This bit will be low for normal
operation.
Table 53 - Transmit Slip Buffer Delay
(Page 3, Address 18H) (T1)
1-0
- - - Unused
Table 51 - Receive Signal Status Word
(Page 3, Address 16H) (T1)
Bit Name
Functional Description
Bit Name
Functional Description
7-0 ID7-0 ID Number. Contains device code
7
TSLIP Transmit Slip. A change of state (i.e.
1-to-0 or 0-to-1) indicates that a
transmit controlled frame slip has
occurred.
10101111
Table 54 - Identification Word
(Page 3, Address 1FH) (T1)
6
TSLPD Transmit Slip Direction. If one,
indicates that the last transmit frame
slip resulted in a repeated frame, i.e.,
the internally generated 1.544 Mhz.
transmit clock is faster than the system
clock (C4b). If zero, indicates that the
last transmit frame slip resulted in a
lost frame, i.e., the internally generated
1.544 Mhz. transmit clock is slower
than network clock. Updated on an
TSLIP occurrence basis.
5
TxSB Transmit Slip Buffer MSB. The most
MSB significant bit of the phase status word.
If one, delay through the transmit
elastic buffer is greater than one frame
in length; if zero, delay through the
receive elastic buffer is less than one
frame in length. Bit is reset whenever
page 3 address 17H - Transmit Slip
Buffer Delay - is written to.
4 - 0
- - - Unused.
Table 52 - MSB Transmit Slip Buffer
(Page 3, Address 17H) (T1)
57
MITEL [ MITEL NETWORKS CORPORATION ]
