MT9074
Advance Information
Bit Name
Functional Description
Bit
Name
Functional Description
7
6
1SEC One Second Timer Status. This bit
7 - 3 RxTS4 - 0 Receive Time Slot. A five bit
counter that indicates the number
of time slots between the receive
elastic buffer internal write frame
boundary and the ST-BUS read
frame boundary. The count is
updated every 250 uS.
changes state once every 0.5 seconds.
2SEC Two Second Timer Status. This bit
changes state once every second and
is synchronous with the 1SEC timer.
5
5SEC Five Second Timer Status. This bit
changes state once every 2.5 seconds
and is synchronous with the 1SEC
timer.
2 - 0 RxBC2 - 0 Receive Bit Count. A three bit
counter that indicates the number
of STBUS bit times there are
between the receive elastic buffer
internal write frame boundary and
the ST-BUS read frame boundary.
The count is updated every 250
uS.
4-0
- - - Unused.
Table 47 - Timer Status Word
(Page 3, Address 12H) (T1)
Table 49 - Least Significant Phase Status Word
(Page 3, Address 14H) (T1)
Bit Name
Functional Description
7
RSLIP Receive Slip. A change of state (i.e.,
1-to-0 or 0-to-1) indicates that a
receive controlled frame slip has
occurred.
Bit
Name
Functional Description
Bit Oriented
Message. This register contains
the eight least significant bits of
the ESF bit oriented message
codeword. The contents of this
register is updated when a new
7 - 0 RxBOM7 - 0 Received
6
RSLPD Receive Slip Direction. If one,
indicates that the last received frame
slip resulted in a repeated frame, i.e.,
the system clock (C4b) is faster than
network clock (E2o). If zero, indicates
that the last received frame slip
resulted in a lost frame, i.e., system
clock slower than network clock.
Updated on an RSLIP occurrence
basis.
bit
-
oriented
message
codeword has been detected in
8 out of the last ten codeword
positions.
Table 50 - Receive Bit Oriented Message
(Page 3, Address 15H) (T1)
5
RxFRM Receive Frame Delay. The most
significant bit of the Receive Slip
Buffer Phase Status Word. If zero, the
delay through the receive elastic
buffer is greater than one frame in
length; if one, the delay through the
receive elastic buffer is less than one
frame in length.
4-0
- - -
Unused
Table 48 - Most Significant Phase Status Word
(Page 3, Address 13H) (T1)
56
MITEL [ MITEL NETWORKS CORPORATION ]
