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MT9074AL 参数 Datasheet PDF下载

MT9074AL图片预览
型号: MT9074AL
PDF下载: 下载PDF文件 查看货源
内容描述: T1 / E1 / J1单芯片收发器 [T1/E1/J1 Single Chip Transceiver]
分类和应用: 电信集成电路
文件页数/大小: 122 页 / 371 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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Advance Information  
MT9074  
Bit  
Name  
Functional Description  
Bit  
Name  
Functional Description  
Unused.  
1
BIOMI  
Bit Oriented Message Interrupt.  
When unmasked this interrupt bit  
goes high whenever a pattern  
111111110xxxxxx0 has been  
received on the FDL that is  
different from the last message.  
The new message must persist for  
7
6
- - -  
HDLC0I HDLC0 Interrupt. Whenever an  
unmasked HDLC0 interrupt occurs  
(from the 4 kHz data link) this bit  
goes high. Reading this register  
clears this bit.  
8
out the last 10 message  
5
4
HDLC1I HDLC1 Interrupt. Whenever an  
unmasked HDLC1 interrupt occurs  
(from the DS1 channel 24  
signalling channel) this bit goes  
high. Reading this register clears  
this bit.  
positions to be accepted as a valid  
new message. Reading this  
register clears this bit.  
0
SIGI  
Signalling  
Interrupt.  
When  
unmasked this interrupt bit goes  
high whenever a change of state  
(optionally debounced - see DBEn  
in the Data Link, Signalling Control  
Word page 1 address 12H) is  
detected in the signalling bits (AB  
or ABCD) pattern. Reading this  
register clears this bit.  
LCDI  
Loop Code Detected Interrupt.  
When unmasked this interrupt bit  
goes high whenever either the  
loop up (00001) or loop down  
(001) code has been detected on  
the line for  
a period of 48  
milliseconds. Reading this register  
clears this bit.  
Table 69 - Interrupt Word Three  
(Page 4, Address 1EH) (T1)  
3
2
1SECI  
5SECI  
One Second Status Interrupt.  
When unmasked this interrupt bit  
goes high whenever the 1SEC  
status bit (page 3 address 12H bit  
7) goes from low to high. Reading  
this register clears this bit.  
Five Second Status Interrupt.  
When unmasked this interrupt bit  
goes high whenever the 5 SEC  
status bit goes from low to high.  
Reading this register clears this  
bit.  
Table 69 - Interrupt Word Three  
(Page 4, Address 1EH) (T1)  
63  
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