MT90220
Address (Hex):
217
Synchronized access The value in this register is used for internal access to the counter when the
transfer command is issued
Reset Value (Hex):
00
Bit #
Type
Description
7:4
R/W
The valid bit combinations are:
1011: UTOPIA Input, counter of all cells for link
1010: UTOPIA Input, counter of Idle cells for link
1001: UTOPIA Input, counter of Unassigned cells for link
1000: UTOPIA Input, counter of cell with HEC error, single or multiple bit error
0111: TX Link, total number of cells,
0110: TX Link, number of Idle/Filler cells,
0101: TX Link, number of Stuff cells,
0100: TX Link, number of ICP cells,
0011: RX Link, total number of cells (or stuff cells),
0010: RX Link, number of Idle/Filler cells,
0001: RX Link, number of cells with HEC errors,
0000: RX Link, number of bad ICP cells.
3:0
R/W
The valid bit combinations are:
1011: IMA Group 3 when UTOPIA Input counter access
1010: IMA Group 2when UTOPIA Input counter access
1001: IMA Group 1when UTOPIA Input counter access
1000: IMA Group 0when UTOPIA Input counter access
0111: Link 7
0110: Link 6
0101: Link 5
0100: Link 4
0011: Link 3
0010: Link 2
0001: Link 1
0000: Link 0
Table 93 - Select Counter Register
Address (Hex):
Synchronized access
Reset Value (Bin):
207
0XX00000
Bit #
Type
Description
7
R/W
Write: 0 for normal operation.
Read: 1 when the transfer is done, 0 when the transfer is pending.
6
5
4
3
R/W
R/W
R/W
R/W
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Reserved, write 0 for normal operation.
Value to write to the Enable bit. 1 to enable, 0 to mask interrupt. This value is transferred
when the bit 1:0 are 10.
2
R/W
R/W
0 will enable the transfer from the uP to the selected counter.
1 will enable the transfer from the selected counter to the uP.
1:0
00: Reserved. Do not use.
01: initiate a read or write of the counter value.
10: initiate a read or write of the IRQ enable counter bit.
11: not used.
Table 94 - Counter Transfer Command Register
74
MITEL [ MITEL NETWORKS CORPORATION ]
