MT90220
Address (Hex):
Direct access
Reset Value (Hex):
09E
1 reg. for all 8 RX links
00
Bit #
Type
Description
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCM TX Sync signal faulty on link 7. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 6. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 5. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 4. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 3. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 2. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 1. Cleared by writing ’0’.
PCM TX Sync signal faulty on link 0. Cleared by writing ’0’.
Table 87 - TX Sync. Status Register
Address (Hex):
Direct access
Reset Value (Hex):
09C
FF
Bit #
Type
Description
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
A ’1’ signifies that the TX Clock, link 7 is disabled.
A ’1’ signifies that the TX Clock, link 6 is disabled.
A ’1’ signifies that the TX Clock, link 5 is disabled.
A ’1’ signifies that the TX Clock, link 4 is disabled.
A ’1’ signifies that the TX Clock, link 3 is disabled.
A ’1’ signifies that the TX Clock, link 2 is disabled.
A ’1’ signifies that the TX Clock, link 1 is disabled.
A ’1’ signifies that the TX Clock, link 0 is disabled.
Table 88 - TX Clock Disabled Status
Address (Hex):
Direct access
Reset Value (Hex):
09D
03
Bit #
Type
Description
7:2
1
R
R
R
Unused. Read 0’ss
A ’1’ signifies that the PLLREF1 Clock is disabled.
A ’1’ signifies that the PLLREF0 Clock is disabled.
Table 89 - PLL REF Clock Disabled Status/Device Rev
0
72