MT90220
7.11 Interrupt Registers Description
Tables 95 to 103 describe the Interrupt registers.
Address (Hex):
Direct access
Reset Value (Hex):
232
00
Bit #
Type
Description
7:0
R
Each bit represents a link. A ’1’ means that the corresponding link has a valid request for
interrupt. The level of the IRQ pin is controlled by the bits in this register and the
corresponding bits in the IRQ Master Enable Register. A write does not have any affect
on the bits in this register. The status bit is not latched and changing the mask bit in the
IRQ Master Register has a direct effect on the level of the IRQ pin.
Table 95 - IRQ Master Status Register
Address (Hex):
Direct access
Reset Value (Hex):
218
00
Bit #
Type
Description
7:0
R/W
Each bit represents a link. A ’1’ means that the interrupt form the corresponding link is
enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master
Register is set. A ’0’ means that the IRQ level is not affected by the corresponding bit.
Table 96 - IRQ Master Enable Register
Address (Hex):
Direct access
Reset Value (Hex):
222 - 229
1 Status register per link
00
Bit #
Type
Description
a
7
R
A ’1’ in this bit means that at least one of the IRQ sources from the IMA Group Overflow
Status Register is requesting service. This bit can be cleared only by service the source of
the IRQ. This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for
the IRQ Link 1-7 Status registers.
b
6
R/W
R/W
A 1 in this bit means that at least one of the Ready bit used to initiate a transfer of a TX ICP
cell for at least 1 of the IMA Group is returned to 1 (meaning that the transfer of the TX ICP
cell is complete) or a frame pulse was detected for an IMA Group. This bit is cleared by
writing a 0 to it. This bit is valid only for the IRQ Link 0 Status register and is reading always
a 0 for the IRQ Link 1-7 Status registers.
5
ICP Cell with changes received. The link has received an ICP cell which contain one or
more changes in it. This status bit can be cleared by writing a ’0’ to it. This bit is set when
an ICP cell is stored in RX ICP cell buffer as defined in RX ICP cell type RAM register 1or 2.
4
3
R/W
R/W
IV. The Link has received an ICP cell which contain a violation as defined in Table 16 of IMA
Spec. This status bit can be cleared by writing a ’0’ to it.
LODS. The Link is Out of Delay Synchronization. This status bit can be cleared by writing a
’0’ to it.
2
1
0
R/W
R/W
R
LIF. Loss of IMA Frame. This status bit can be cleared by writing a ’0’ to it.
LCD Loss of Cell Delineation. This status bit can be cleared by writing a ’0’ to it.
Link Counter Overflow Interrupt. One or more counters associated with the link overflowed.
This status bit can be cleared only by reading or writing to the counter(s) which is (are) the
source for the IRQ.
Table 97 - IRQ Link Status Registers
a. Bit 7 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
b. Bit 6 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
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MITEL [ MITEL NETWORKS CORPORATION ]
