MT90220
7.12 Miscellaneous Registers Description
Tables 104 to 106 describe the General Status and Test Register.
Address (Hex):
Direct access
Reset Value (Hex):
206
10
Bit #
Type
Description
7:4
3
R
Device Revision Number: reads 0001.
R/W
Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared by
writing a 0.
2
R/W
Set when the UTOPIA input clock is missing or too slow. This latched bit is cleared by
writing a 0.
1
0
R/W
R/W
Overflow of 1 or more of the TX UTOPIA FIFO.
Set when there is no free cell in TX Cell RAM. This latched bit is cleared by writing a 0.
Table 104 - General Status Register
Address (Hex):
Direct access
Reset Value (Hex):
O4E
00
Bit #
Type
Description
7:0
7:0
R
Reserved (different than written values).
Write 0x60 for normal operation.
Table 105 - Test 1 Register
W
Address (Hex):
Direct access
Reset Value (Hex):
0DA
00
Bit #
Type
Description
7:0
7
R
Reserved (different from written values).
Write 0 for normal operation.
W
W
W
W
6
Write 1 for normal operation.
5:4
3
Write 00 for normal operation
Write 1 before adding a link to an existing IMA group.
Write 0 when the link is reported in IMA mode.
2
W
W
Write 0 for normal operation.
1:0
Write IMA group number before adding a link to an IMA group.
Table 106 - Test 2 Register
78
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