MT90220
Address (Hex):
Direct access
Reset Value (Hex):
088 - 08F
1 reg. per TX link
00
Bit #
Type
Description
7
R/W
PCM port tri-state control. TXCLK, TXSYNC and DSTO outputs are active when the bit is
1. The outputs of the Port is in tri-state if the bit is 0.
6:5
R/W
00: T1, Generic Mode, 1.544MHz or 2.048 MHz Clk, (Mode 1 or 5)
01: T1, ST-BUS Mode, 4.096MHz Clk, (Mode 2 or 6)
10: E1, Generic Mode, 2.048 MHz clk, (Mode 3 or 7)
11: E1, ST-BUS Mode, 4.096MHz Clk, (Mode 4 or 8)
The direction of the TXCK and TXSYNC signals (i.e.; input or output) is defined using the
TX PCM Link Control register #2 bit 4.
4
3
R/W
R/W
This bit defines the PCM clock rate when one of the 2 T1 generic modes is selected. A 1
signifies that a 2.048 MHz clock is used and a 0 signifies that a 1.544 MHz clock is used.
This bit is valid only for T1 Generic modes (PCM Mode 1 or 5).
This bit defines the position of the PCM channels over the PCM Stream. A value of 1
means that the 24 channels are grouped and transmitted in the first 24 channels on the
PCM stream. A value of 0 corresponds to using 3 channels every 4 channels. This bit is
valid only for T1 type link, in ST-BUS or Generic mode with a TXCK frequency of
2.048MHz. It is not applicable for T1, Generic mode with TXCK frequency of 1.544MHz.
2
1
0
R/W
R/W
R/W
T1 Signaling channel. A value of 1 disables the use of the channel 24 and reserves it for
signaling. A value of 0 enables the use of the 24 channels to carry the cells. Valid only for
T1 mode.
TX Clock polarity: Rising edge of TXCK is used to output new data on DSTo if bit is 1.
Falling edge of TXCK is used to output new data on DSTo if bit is 0. Valid in Generic PCM
mode only
TX frame pulse polarity. Positive if bit is 1, negative if bit is 0. Valid in Generic PCM mode
only.
Table 82 - TX PCM Link Control Register Number 1
68
MITEL [ MITEL NETWORKS CORPORATION ]
