MT90220
7.9 TX/RX and PLL Control Registers Description
Tables 81 to 89 describe the TX/RX and PLL Control registers.
Address (Hex):
Direct access
Reset Value (Hex):
080 - 087
1 reg. per TX link
00
Bit #
Type
Description
7:5
4
R
Unused. Read all 0’s.
R/W
TXCK and TXSYNC Direction:
When the bit is 0 (default value)
Mode 1: TXCK and TXSYNC are outputs
Mode 2: TXCK and TXSYNC are inputs
Mode 3: TXCK and TXSYNC are outputs
Mode 4: TXCK and TXSYNC are inputs
When the bit is 1
Mode 5: TXCK and TXSYNC are inputs
Mode 6: TXCK and TXSYNC are outputs
Mode 7: TXCK and TXSYNC are inputs
Mode 8: TXCK and TXSYNC are outputs
3:0
R/W
These 4 bits are used to select the source for the TXCK for the link:
The valid combinations are:
0000: RXCK0
0001: RXCK1
0010: RXCK2
0011: RXCK3
0100: RXCK4
0101: RXCK5
0110: RXCK6
0111: RXCK7
1000: REFCK0
1001: REFCK1
1010: REFCK2
1011: REFCK3
Table 81 - TX PCM Link Control Register Number 2
67
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