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MT90220 参数 Datasheet PDF下载

MT90220图片预览
型号: MT90220
PDF下载: 下载PDF文件 查看货源
内容描述: 八IMA / UNI PHY设备 [Octal IMA/UNI PHY Device]
分类和应用:
文件页数/大小: 116 页 / 305 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT90220  
ST-BUS  
Bit Cells  
(DSTx0-7)  
...  
Channel 31 bit 0  
Bit Cell  
Channel 0 bit 7  
Channel 0 bit 0  
Channel 1 bit 7  
Bit Cell  
...  
Unused or  
High Impedance  
Unused or  
High Impedance  
Serial Bit  
Stream  
...  
...  
...  
...  
TXSYNC  
RXSYNC  
TXCK  
RXCK  
...  
...  
...  
...  
ST-BUS  
Bit Cells  
(DSTx0-7)  
Channel 15 bit 0  
Bit Cell  
Channel 16 bit 7  
Channel 16 bit 0  
Channel 17 bit 7  
Bit Cell  
Unused or  
High Impedance  
Unused or  
High Impedance  
Serial Bit  
Stream  
...  
...  
...  
...  
...  
...  
TXSYNC  
RXSYNC  
TXCK  
RXCK  
Figure 11 - PCM Mode 4 and 8: ST-BUS Interface for E1  
E1 Time-Slots  
-
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15  
10 11 12 13 14 15  
Voice/Data Channels  
(DSTi/o)  
0
x
E1 Time-Slots  
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30  
Voice/Data Channels  
(DSTi/o)  
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
x
Table 10 - Channel Mapping from ST-BUS to E1  
1, the TXCK and TXSYNC pins are outputs. In the  
PCM Mode 5, the TXCK and TXSYNC pins are  
defined as inputs.  
of the PCM frame (i.e., the T1 framing bit) to perform  
the G.804 recommended transmission convergence  
function (see Figure 12). This frame bit is also  
ignored on the receive side. The position of the  
frame bit is indicated by the TXSYNC and RXSYNC  
signals.  
4.2.3.1 1.544 MHz Clock  
In this sub-mode, (selected by clearing the bit 4 of  
the TX PCM Control Register 1,) the serial PCM  
Interface rate is equal to the line bit rate. When  
selected to operate in this sub-mode, the interface  
clock is 1.544 MHz and the DSTo and DSTi the data  
lines transport only 24 time-slots plus the DS1  
framing bit for a total of 193 bits per frame.  
4.2.3.2 2.048 MHz Clock  
In this sub-mode (selected by setting the bit 4 of the  
TX PCM Control Register 1) the channel/timeslot  
mapping for this mode is similar to the ST-BUS mode  
for T1. The same PCM mapping schemes (grouped  
or spaced) are supported. The TXCLK and RXCLK  
are 2.048 MHz signal and the TXSYNC and  
RXSYNC are a frame pulse of one full bit duration  
that occurs at the beginning of the frame. The frame  
rate is 8 KHz. The polarity of the TXCK, RXCK,  
TXSYNC and RXSYNC and their active edge is  
programmable using TX PCM Link Control register  
number 1 and RX PCM Link Control register.  
The frequency value for TXSYNC and RXSYNC is 8  
kHz. The frequency for the TXCK and RXCK is 1.544  
Mhz.  
The edge of the RXCK and TXCK signals used to  
sample incoming data and transmit the outgoing data  
is fully programmable on a per link basis. This allows  
the MT90220 to operate with the majority of available  
off-the-shelf T1 framers.  
4.2.4 Mode 3 and 7: Generic PCM Interface for E1  
The channel/timeslot mapping in this mode is similar  
to the ST-BUS mode for E1. The differences are:  
When operating in the generic PCM system Interface  
at 1.544 MHz, the MT90220 does not use the first bit  
27  
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