MT90220
control. Refer to Section 8, Application Notes, for
examples.
marked by the UTOPIA SOC sync signal. This signal
is active during the transfer of the first byte of a cell.
The 52 bytes that follow the arrival of the first byte of
a cell are interpreted as belonging to the same cell
and are stored accordingly (note that SOC sync
signals received during the loading of these 52 bytes
are ignored).
4.3.4 Verification of Clock Activity
The MT90220 implements circuitry to determine
whether or not a selected clock signal is active. This
feature is used to ensure a clock is operational
before using it as a source for one or more transmit
links. The identity of the clock source to be verified is
written to the Clock Activity register. A read of the
same register indicates clock activity if bit 7 is ’1’. A
value of ’0’ for bit 7 means that no transition was
observed on this clock. This circuitry does not
measure the frequency of a clock signal, it only
detects activity on the eight RXCK, eight TXCK and
four REFCK signals.
The cell available satus line (Clav) is used to
communicate to the ATM controller if the MT90220
has space for a cell in the PHY address that was
polled in the previous cycle. Whenever there is
space for a cell in teh TX direction or a cell ready in
the RX direction, the TXClav and/or RXClav signal
will be driven High or Low. When the address does
not correspond to any enabled PHY address inside
the MT90220, the TXClav and RXClav signal are in
High impedance mode. The use of an external pull-
down may be required for the proper operation of the
Utopia bus in MPHY mode.
4.3.5 Clock Selection
In normal operation, the clock selection circuitry
selects the desired clock signal and ensures a
smooth, glitch free, transition between the current
clock source and the new clock source.
It should be noted that the bit 6 and 5 of the Test 1
register have to be set to 1 for the proper operation
of the RX Utopia port in MPHY mode.
However, if the current clock source is inactive (i.e.,
no clock transitions), the clock select circuitry must
be reset before another clock can be used as
reference. Clock select circuitry is reset by writing a
1 to bit 7 of the PLL Reference Control register.
Clock source activity can be verified using the Clock
Activity register as described in 4.3.4 Verification of
Clock Activity.
5.1 ATM Input Port
The UTOPIA interface input clock TxClk is
independent of the system clock. The UTOPIA TxClk
can be up to 25MHz. The incoming cell is stored
directly in the internal TX Cell RAM where the TX
UTOPIA FIFOs are implemented.
The TX byte clock (TxClk) can be up to 25 MHz and
is checked against the system clock. If the incoming
byte clock frequency is lower than 1/128 of the
system clock, bit 2 of the General Status register
will be set. This bit is cleared by overwriting it with 0.
5.0 UTOPIA Interface Operation
The MT90220 supports the UTOPIA L2 Mode for cell
level handshake only. Each port can be assigned an
address ranging from 0 to 30. The address value of
31 is reserved and should not be used for any
MT90220 port.
The total space for the UTOPIA input cells for all IMA
Groups and links in UNI mode is 58. These 58 cells
are shared between 12 TX UTOPIA FIFOs and 8 TX
Link FIFOs. The size (length) of each TX UTOPIA
FIFO is defined by writing to the TX UTOPIA FIFO
Length Definition registers. The maximum value is
15 and the minimum value is 0 (in the case the PHY
port is not to be used). The size of the TX Link FIFO
is defined on a per group using the TX IMA Control
registers.
The TX and RX paths of each IMA Group and each
link in UNI has its own PHY address. These PHY
addresses are defined in the UTOPIA Input link
Address registers 1 to 8, UTOPIA Input Group
Address register 1 to 4, UTOPIA Output link
Address registers 1 to 8, and the UTOPIA Output
Group Address registers 1 to 4. The UTOPIA Input
LINK PHY Enable and the UTOPIA Output Link
PHY Enable registers are used to enable the PHY
Address of the links in UNI. The UTOPIA Input
Group PHY Enable register and the UTOPIA
Output Group PHY Enable registers are used to
enable the PHY Address of the IMA Groups.
The device will not accept a cell from the UTOPIA
Interface if the internal Cell Ram is full. Status bit 0 in
the General Status register is set to 1 to indicate the
’no free cell in TX Cell RAM’ condition. The status bit
can be cleared by overwriting it with 0.
The MT90220 port uses handshaking signals to
process data streams. The start of a cell (SOC) is
The UTOPIA Input block has the option to verify the
HEC of the cell coming from the ATM layer. Four
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