MT90220
T1 Frame
Bit Cells
at DSTx0-7
...
bit 2
bit 193
Bit Cell
bit 1
Serial Bit
Stream
Unused or
High Impedance
...
...
Bit Cell
TXSYNC
TXCK
...
RXSYNC
RXCK
...
Figure 12 - Mode 1 and 5: Generic PCM Interface for T1
•
•
the interface clocks (RXCK and TXCK) operate
at 2.048 MHz only
can be any of the eight RXCK signals or four external
REFCK inputs (see Figure 14). The TXSYNC is
generated from the TXCK signal.
the synchronization signals (TXSYNC and
RXSYNC) are valid for one clock cycle (488
nsec) during the first bit of the frame
The RXCK pins are always defined as inputs and the
proper signal must be provided to each input.
•
•
In PCM Mode 3, the TXCK and TXSYNC pins
are defined as outputs.
4.3.1 Verification of the RXSYNC Period
In PCM Mode 7, the TXCK and TXSYNC are
defined as inputs.
The RXSYNC signal is used to align the incoming
DSTi data to retrieve all the T1 or E1 channels. The
RXSYNC pulse can be present for each PCM frame
(8Khz) or once per Superframe (every 12 or 24 PCM
frames). The period and position of the RXSYNC is
verified for each receive block independently. A status
bit (1 per link) in the RX Sync Status register is set if
the synchronization pulse occurs at an unexpected
time in the frame. The RX block will be re-aligned with
this new synchronization pulse.
The edge of the RXCK and TXCK signals that is
used to sample the incoming, and transmit the
outgoing, data is fully programmable on a per link
basis. This allows the MT90220 to operate with the
majority of off-the-shelf E1 framers.
The MT90220 does not use timeslots 0 and 16 to
perform the G.804 transmission convergence
function (see Figure 13).
4.3.2 Verification of the TXSYNC Period
4.2.5 TXSYNC Signal in Mode 5 and 7
The TXSYNC signal is used to align the outgoing
DSTo data to retrieve all the T1 or E1 channels.
When defined as input, the TXSYNC pulse can be
present for each PCM frame (8Khz) or once per
Superframe (every 12 or 24 PCM frames). The
period and position of the TXSYNC is verified for
each transmit block independently. A status bit (1 per
link) in the TX Sync Status register is set if the
synchronization pulse occurs at an unexpected time
in the frame. The TX block will be re-aligned with this
new synchronization pulse.
The TXSYNC signal is defined as an input in PCM
mode 5 and 7 and is sampled at the bit boundary. A
positive delay of 10 nsec is expected between the
TXCLK signal at the bit boundary and the time the
TXSYNC changes. This may cause some inter-
operability problems when the MT90220 is
connected to some off-the-shelf framers as the
TXSYNC can be slightly ahead of the TXCLK signal.
In this case, the TXSYNC signal need to be delayed
to ensure proper operation of the TX PCM port.
4.3.3 Primary and Secondary Reference Signals
4.3 Clocking Options
Two output pins are provided to simplify the external
circuitry required when using an external PLL. These
two pins, PLLREF0 and PLLREF1, re-route any of
the eight RXCK signals and drive the primary and
secondary reference signals of a PLL under software
In PCM Modes 2, 4, 5 and 7, the TXCK and TXSYNC
are inputs and are generated by external circuitry.
In PCM Modes 1, 3, 6 and 8, the TXCK and TXSYNC
are outputs. TXCK source is software selectable and
28
MITEL [ MITEL NETWORKS CORPORATION ]
