MT90220
RXCK
RXSYNC
DSTi
Idle Cell
Removal
Cell
Delineation
S/P
S/P
S/P
S/P
RXCK
RXSYNC
DSTi
Idle Cell
Removal
Cell
Delineation
UTOPIA
Interface
RXCK
RXSYNC
DSTi
Idle Cell
Removal
Cell
Delineation
RXCK
RXSYNC
DSTi
Idle Cell
Removal
Cell
Delineation
System Clock
Figure 8 - Example of UNI Mode Operation
(Using Four of Eight Possible UTOPIA-Output Ports)
•
•
using ST-BUS and Generic PCM modes
4.0 Description of the PCM Interface
enabling/disabling the P/S and S/P units (if they
are disabled the associated outputs are Tri-
stated)
To provide support for the IMA Asymmetrical mode,
the Transmit PCM blocks are independent from the
Receive PCM blocks. The TX port of a framer can be
connected to any of the MT90220 TX UTOPIA Input
ports and the RX port of a framer can be connected
to any of the MT90220 RX UTOPIA Output ports.
•
•
mapping T1 links, on a per port and per
direction basis, to use either the first 24
channels or 3 of every 4 channels (when ST-
BUS or 2.048 clock modes are selected)
programming T1 links to ignore timeslot 24 and
reserve it for signaling (since only 23 timeslots
are used to carry the ATM cells, this option
should be applied to all links of the same IMA
Group)
4.1 Serial to Parallel (S/P) and Parallel to Serial
(P/S) Converters
Each T1/E1 link has a S/P and P/S unit assigned.
The P/S unit takes a byte from the cell RAM and
converts it to a serial bit stream. The S/P unit takes a
byte from the DSTi input and converts it to parallel
format for use by the Cell Delineation block.
•
•
•
independently programming the polarity of
RXCK, TXCK, RXSYNC and TXSYNC signals
(Generic PCM mode only)
generating/accepting TXSYNC and TXCLK
signals to support most T1 and E1 framers
(depending on the programmed mode)
The system interface supports both the ST-BUS
(2.048 Mbps bus) and generic PCM Interface. Note
that the ST-BUS is compatible with the so-called
MVIP mode that is supported by some T1 or E1
framer manufacturers.
monitoring RXSYNC signal period and
reporting the unexpected occurrence of a
synchronization signal (see 4.3.1 Verification of
the RXSYNC Period, for more details)
•
monitoring TXSYNC signal period (when
defined as input) and reporting the unexpected
occurrence of a synchronization signal (see
4.3.2 Verification of the TXSYNC Period, for
more details)
The MT90220 generates and receives the PCM
channels only (24 or 23 with T1, 30 with E1). The
control/status channels of the framers and the
signaling channels are not supported by the
MT90220.
•
•
generating a TXSYNC pulse on every PCM
frame when defined as output
P/S and S/P units can be set-up differently on a per
port and per direction basis (i.e. the transmit and
receive function of the same port can use different
assigning any TX or RX link to any IMA Group
When the TXCK and TXSYNC signals are outputs,
the source for the TXCLK is software selectable from
any of the eight RXCK inputs or any of the four
external REFCKs. The TXSYNC signal is generated
configurations).
supported:
The
following
features
are
•
programming links as T1 or E1
23
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