MT90220
DS1 Time slots
1
0
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
1
0
1
1
1
2
1
3
1
4
1
5
1
6
Voice/Data Channels
(DSTi/o)
9
1
0
1
1
1
2
1
3
1
4
1
5
ST-BUS
DS1 Time slots
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
-
-
-
-
-
-
-
-
Voice/Data Channels
(DSTi/o)
ST-BUS
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
x
2
5
x
2
6
x
2
7
x
2
8
x
2
9
x
3
0
x
3
1
x
Table 9 - T1 Channel Mapping Using 24 Consecutive Channels
Bit Cells
at DSTx0-7
...
...
Channel 31 bit 0
Channel 0 bit 7
Bit Cell
Channel 0 bit 6
Bit Cell
Channel 23 bit 0
Bit Cell
Channel 24 bit 7
Serial Bit
Stream
Unused or
High Impedance
Unused or
...
...
...
...
High Impedance
TXSYNC
RXSYNC
TXCK
RXCK
...
...
Figure 10 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Grouped Mapping)
BUS Clock signal (i.e., 4.096 MHz). The TXSYNC
signal is generated by the MT90220 and meets the
ST-BUS format. It is not synchronized with any other
RXSYNC or TXSYNC signal.
(DS1) frame. This last channel is reserved for
signaling.
4.2.2 Mode 4 and 8: ST-BUS lnterface for E1
4.2.1.1 Detailed ST-BUS Spaced Mapping
(3 of Every 4 Channels)
The MITEL ST-BUS has 32 channels, numbered 0 to
31. The PCM-30 payload is mapped to 30 of the 32
ST-BUS timeslots. Channels 0 and 16 are used for
framing and signaling information. See Figure 11
and Table 10.
DS1 (T1) links contain 24 bytes of serial voice/data
channels distributed over the 32 ST-BUS channels.
One mapping option uses 3 of every 4 channels. The
channels 0, 4, 8, 12, 16, 20, 24 and 28 of the ST-
BUS are not used. The MT90220 tri-states the DSTo
lines during the unused time-slots. See Figure 9.
In E1 PCM Modes 4 and 8, the MITEL ST-BUS clock
value is 4.096 MHz. The frame pulse is 8 kHz and
should be as defined in Figure 11.
4.2.1.2 Detailed ST-BUS Grouped Mapping
(24 Consecutive Channels)
In PCM Mode 4, the TXCK and TXSYNC pins are
defined as inputs and are generated by external
circuitry. In the PCM Mode 8, the TXCK and
TXSYNC pins are defined as outputs. The source for
the TXCK is selected using TX PCM Link Control
register number 2 and can be any of the eight RXCK
or four external REFCK clocks. As there is no PLL
inside the MT90220, the source frequency has to be
a valid ST-BUS Clock signal (i.e., 4.096 MHz). The
TXSYNC signal is generated by the MT90220 and
meets the ST-BUS format. It is not synchronized with
any other RXSYNC or TXSYNC signal.
In this option, the 24 bytes of serial voice/data
channels of the DS-1 use the first 24 consecutive
channels over the 32 ST-BUS channels. The
MT90220 tri-states the DSTo lines for the unused
channels (25 - 31). Refer to Table 9.
4.2.1.3 Detailed ST-BUS ISDN Mapping
(T1 ISDN Modes)
When the T1 ISDN modes are selected, channel 24
is not used to carry bytes from ATM cells. This byte is
not used in the receive direction. In the transmit
direction it is set to a high impedance state. The ST-
BUS mapping is identical as in the T1 (DS1) ’clear
channel’ set-up except for the last channel of the T1
4.2.3 Mode 1 and 5: Generic PCM Interface for T1
In PCM Modes 1 and 5, the TXCK clock frequency
can be either 1.544 or 2.048 MHz. In the PCM Mode
26
MITEL [ MITEL NETWORKS CORPORATION ]
