MT8931C
BIT
NAME
DESCRIPTION
A ’1’ will enable the D-channel collision interrupt.
B7
EnDcoll
A ’0’ will disable it. This bit is available only in TE mode.
B6
B5
B4
B3
B2
B1
B0
EnEOPD A ’1’ will enable the received End of Packet interrupt.
A ’0’ will disable it.
EnTEOP A ’1’ will enable the transmit End of Packet interrupt.
A ’0’ will disable it.
EnFA
A ’1’ will enable the Frame Abort interrupt.
A ’0’ will disable it.
EnTxFL
A ’1’ will enable the Transmit FIFO Low interrupt.
A ’0’ will disable it.
EnTxFun A ’1’ will enable the Transmit FIFO Underrun interrupt.
A ’0’ will disable it.
EnRxFF
A ’1’ will enable the Receive FIFO Full interrupt.
A ’0’ will disable it.
EnRxFov A ’1’ will enable the Receive FIFO Overflow interrupt.
A ’0’ will disable it.
Table 9. HDLC Interrupt Mask Register (Write Add. 00100B)
BIT
NAME
DESCRIPTION
B7
Dcoll(1)
A ’1’ indicates that a collision has been detected on the D-channel (i.e., received E-bit
does not match with transmitted D-bit). This bit is available only in TE mode and when the
HDLC transmitter is enabled. It always reads ’0’ in NT mode.
B6
B5
B4
B3
B2
B1
B0
EOPD(1)
TEOP(1)
FA(1)
A ’1’indicates that an end of packet has been detected on the HDLC receiver. This can be
in the form of a flag, an abort sequence or as an invalid packet.
A ’1’ indicates that the transmitter has finished sending the closing flag of the last packet in
the Tx FIFO, and the internal priority level is reduced from high to low.
A ’1’ indicates that the receiver has detected a frame abort sequence on the received data
stream.
TxFL(1)
TxFun(1)
RxFF(1)
RxFov(1)
A ’1’ indicates that the device has only four Bytes remaining in the Tx FIFO. This bit has
significance only when the Tx FIFO is being depleted and not when it is getting loaded.
A ’1’ indicates that the Tx FIFO is empty without being given the ’end of packet’ indication.
The HDLC will transmit an abort sequence after encountering an underrun condition.
A ’1’ indicates that the HDLC controller has accumulated at least 15 bytes in the Rx
FIFO.
A ’1’ indicates that the Rx FIFO has overflown (i.e., an attempt to write to a full Rx FIFO).
The HDLC will always disable the receiver once the receive overflow has been detected.
The receiver will be re-enabled upon detection of the next flag.
Table 10. HDLC Interrupt Status Register (Read Add. 00100B)
Note 1:
All interrupts will be reset after a read to the HDLC Interrupt Status Register.
9-90
MITEL [ MITEL NETWORKS CORPORATION ]
