MT8931C
3) If the HDLC transmitter is in transparent
data mode, the protocol functions are disabled
and the data in the transmit FIFO is transmitted
without a framing structure.
set HIGH, before writing the next byte into the FIFO.
This bit is cleared automatically once the byte is
written to the Transmit FIFO. When the ‘flagged’
byte reaches the bottom of the FIFO, a frame abort
sequence is sent instead of the byte and the
transmitter operation returns to normal. The frame
abort sequence is ignored if the packet has less then
two bytes.
To indicate that the particular byte is the last byte of
the packet, the EOP bit in the HDLC Control Register
2 must be set before the last byte is written into the
transmit FIFO. The EOP bit is cleared automatically
when the data byte is written to the FIFO. After the
transmission of the last byte in the packet, the frame
check sequence (16 bits) is sent followed by a
closing flag. If there is any more data in the transmit
FIFO, it is immediately sent after the closing flag.
That is, the closing flag of a packet is also used as
the opening flag the the next packet.
iii) Transparent Data Transfer
The Trans bit (B4) in the HDLC Control Register 2
can be set to provide transparent data transfer by
disabling the protocol functions. The transmitter no
longer generates the Flag, Abort and Idle sequences
nor does it insert the zeros and calculate the FCS.
However, CCITT I.430 and ANSI T1.605
Recommendations state that after the successful
transmission of a packet, a TE must lower its priority
level within the specified priority class. The user can
meet this requirement by loading the Tx FIFO with no
more than one packet and then waiting for the DCack
bit to go to zero, or for an HDLC interrupt by the
TEOP bit in the HDLC Interrupt Status Register,
before attempting to load a new packet. If there is no
more data to be transmitted, the transmitter assumes
the selected link channel state.
It should be noted that none of the protocol related
status or interrupt bits are applicable in transparent
data transfer state. However, the FIFO related status
and interrupt bits are pertinent and carry the same
meaning as they do while performing the protocol
functions.
HDLC Receiver
After a reset on power up, the receive section is
disabled. Address detection is also disabled when a
reset occurs. If address detection is required, the
Receiver Address Registers are loaded with the
desired address and the ADRec bit in the HDLC
Control Register 1 is set HIGH. The receive section
can then be enabled by RxEN bit in this same
Control Register 1. All HDLC interrupts are masked,
thus the desired interrupt signal must be unmasked
through the HDLC Interrupt Mask Register. All active
interrupts are cleared by reading the HDLC Interrupt
Status Register.
During the transmission of either the data or the
frame check sequence, the Protocol Controller
checks the transmitted information on a bit by bit
basis to insert a ZERO after every sequence of five
consecutive ONEs. This is required to eliminate the
possibility of imitating the opening or closing flag, the
idle code or an abort sequence.
i) Transmit Underrun
A transmit underrun occurs when the last byte
loaded into the transmit FIFO was not ‘flagged’ with
the ‘end of packet’ (EOP) bit and there are no more
bytes in the FIFO. In such a situation, the Protocol
Controller transmits the abort sequence (zero and
seven ones) and moves to the selected link channel
state.
i) Normal Packets
After initialization as explained above, the serial data
starts to be clocked in and the receiver checks for
the idle channel and flags. If an idle channel is
detected, the ‘Idle’ bit in the HDLC Status Register is
set HIGH. Once a flag is detected, the receiver
synchronizes itself in a bytewide manner to the
Conversely, in the event that the transmit FIFO is full,
any further writes will overwrite the last byte in the
Transmit FIFO.
incoming data stream.
The receiver keeps
resynchronizing to the flags until an incoming packet
appears. The incoming packet is examined on a
bit-by-bit basis, inserted zeros are deleted, the FCS
is calculated and the data bytes are written into the
19 byte Receive FIFO. However, the FCS and other
control characters, i.e., flag and abort , are never
stored in the Receive FIFO. If the address detection
is enabled, the address field following the flag is
compared to the bytes in the Receive Address
ii) Abort Transmission
If it is desired to abort the packet currently being
loaded into the transmit FIFO, the next byte written to
the FIFO should be ‘flagged’ to cause this to happen.
The FA bit of the HDLC Control Register 2 must be
9-85
MITEL [ MITEL NETWORKS CORPORATION ]
