ACE9030
ELECTRICAL CHARACTERISTICS
These characteristics apply over these ranges of conditions (unless otherwise stated):
TAMB = – 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = VSS
A.C. Characteristics
Parameter
CONTROL BUS
Clock rate CL input
Clock duty cycle CL input
tDS, input data set-up time
tDH, input data hold time
tCWL, tCWH, CL input pulse width (to bus logic)
tCL, delay time, clock to latch
tLW, latch pulse high time
tLH, delay time, latch to clock
tDSO, output data set-up time
tDHO, output data hold time
tZS, DATA line available to ACE9030
tZH, DATA line released by ACE9030
tCD, delay from received message to
transmitted response
Rise and Fall times, all digital inputs:
DIGITAL OUTPUTS
Min.
Typ.
Max.
60
Unit
Conditions
1008
50
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
of CL
ns
40
80
80
400
440
230
220
80
80
80
80
4
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 8
See Fig. 8
See Fig. 8
See Fig. 8
600
1200
1200
4
See Figs. 8 and 10
50
DOUT0 and 1 On time to VDD – 0·2 V
DOUT0 and 1 Off time to > 1 MΩ
DOUT5, 6 and 7 rise and fall times
DOUT8 rise and fall time
100
100
10
µs
µs
µs
µs
100 nF load and from
LATCHB rising edge
30 pF load and to D.C.
specification noise
10
A to D CONVERTER
Lowest transition, 0000 0000 to 0000 0001
Highest transition, 1111 1110 to 1111 1111
ADC conversion time (20 cycles of CL)
Input scanning rate (CL ÷ 40)
Integral Non-linearity
0·07
3·35
0·15
3·45
20
0·23
3·55
V
V
µs
Bandgap multiplier
correctly trimmed
CL = 1008 kHz
25·2
kHz
CL = 1008 kHz
– 1
– 0·8
+ 1
+ 0·8
3
LSB
LSB
LSB/0.3V
Differential Non-linearity
Power supply sensitivity
0 to 10 kHz
CRYSTAL OSCILLATOR
Start-up time of crystal oscillator
Crystal effective series resistance (ESR)
Power dissipation in crystal
5
25
150
ms
Ω
µW
50
D to A CONVERTERS
Full scale output level, DAC1, DAC2 & DAC3
Zero scale output level, DAC1
Zero scale output level, DAC2 & DAC3
Integral Non-linearity
3·35
1·0
0·3
– 1
– 0·5
3·45
3·55
1·2
0·5
+ 1
+ 0·5
V
V
V
LSB
LSB
Bandgap multiplier
trimmed to nominal
reference voltage
Differential Non-linearity
Output wideband and clock noise:
50 Hz to 1·1 MHz, flat integration
Power supply rejection ratio
Settling time to within 10% of end of step
(DAC3 with external 15 kΩ resistor)
Output load capacitance, DAC1 and DAC2
Output load capacitance, DAC3
Internal series resistor, DAC1 and DAC2
DAC3 output current, sink or source
3
6
mVrms
dB
µs
30
50 Hz to 25 kHz.
DAC1 and DAC2
10 pF load
100
30
40
nF
pF
kΩ
mA
To guarantee stability
7
1·0
15
7
MITEL [ MITEL NETWORKS CORPORATION ]
