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ACE9030MIWFP2Q 参数 Datasheet PDF下载

ACE9030MIWFP2Q图片预览
型号: ACE9030MIWFP2Q
PDF下载: 下载PDF文件 查看货源
内容描述: 无线接口和双合成器 [Radio Interface and Twin Synthesiser]
分类和应用: 无线
文件页数/大小: 39 页 / 382 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ACE9030  
FUNCTIONAL DESCRIPTION - CONTROL BUS  
The functions of the ACE9030 fall into two separate  
groups, the Radio Interface and the Synthesisers.  
The common control bus splits the input strings differ-  
ently for these two sections so this bus operation is described  
first as an introduction to the available features.  
All functions are controlled by a serial bus; DATA is a bi-  
directional data line, to input all control data and to output the  
results of measurements in the Radio Interface section, CL is  
the clock, and LATCHB and LATCHC are the latch signals at  
the end of each control word for either the Radio Interface or  
the Synthesiser section respectively.  
CL is a continuously running clock at typically 1·008 MHz,  
and all incoming and output data are latched on rising edges  
of this clock. The controller should clock data in and out on  
falling clock edges. For bus control purposes the frequency of  
CL may be widely varied and this clock does not need to be  
continuous, however, the sampled I.F. signal AFCOUT, the  
Polling ADC, and the Lock Detect Filter also use CL as the  
sampling clock. In systems where any of these are required  
the clock CL is constrained to be 1·008 MHz and to be  
continuous.  
To ensure clean initialisation the clock CL should give at  
least 8 cycles before the power-up command and similarly to  
set the control logic to known states there should be 8 cycles  
of CL after a power-down command.  
During normal operation there should be at least 30  
cycles of CL between latch pulses, 24 for the data bits (see  
figures 9,10 & 11) plus 6 extra. This minimum becomes 36  
cycles if the extended synthesiser programming command  
(A2) is used.  
Radio Interface Bus - Receive  
CL  
DATA1  
DATA2  
DATA3  
DATA  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0  
LATCHB  
Fig.9 Radio Interface receive bus timing  
andtheCLK8outputdriverwillbeactive, andareusedtoclock  
the microcontroller. To reduce the supply current to its mini-  
mum in Sleep the synthesisers must also be powered down,  
by a Word D message with DA and DM both set HIGH as  
described under Synthesiser Bus - Receive Only. During  
Sleep all set-up values are retained unless changed by a Set-  
upcommand. TheexitfromSleepisbyanyNormalcommand.  
Normal commands will end Sleep mode but are primarily  
used to change the operating mode of the cellular terminal or  
to request ADC data. The ACE9030 will output data onto the  
serial bus after a Normal command.  
The received data is split into three bytes, where DATA1  
normally contains a value to be loaded into a destination set  
by DATA2 and DATA3. When a command does not need to  
put any information into byte DATA1 a preamble xx1010xx is  
recommended to fill this byte. It is possible to set-up several  
features in one bus operation and to allow this the decoding  
only acts on single or selected bits; the others are given as “x”  
in the block descriptions. Two bits of DATA2 also set the type  
of command, with four options:  
DATA2  
DATA2 Type of  
Comment  
Set-up commands are used to adjust various operating  
parameters but can also initiate a logic restart if DATA3 bits 1  
and 0 are both “1” so for routine changes of set-ups these bits  
should always be 00.  
bit 7  
bit 6  
Command  
SLEEP  
NORMAL Send requested data  
SET-UP  
TEST  
0
0
1
1
0
1
0
1
No reply  
No reply  
No reply  
Test mode is included only for use during chip manufac-  
ture.  
The Sleep Command - DATA2 bits 7, 6 = 00  
Sleep mode is selected to put the cellular terminal into a  
very low power state for when it is “Off” and neither waiting for,  
nor setting up a call. In Sleep only the crystal and 8·064 MHz  
oscillators, DAC1 and DAC2, the OSC8 phase locked loop,  
DATA1  
DATA2  
DATA3  
xx1010xx  
00xxxxxx  
xxxxxxxx  
11