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ACE9030MIWFP2Q 参数 Datasheet PDF下载

ACE9030MIWFP2Q图片预览
型号: ACE9030MIWFP2Q
PDF下载: 下载PDF文件 查看货源
内容描述: 无线接口和双合成器 [Radio Interface and Twin Synthesiser]
分类和应用: 无线
文件页数/大小: 39 页 / 382 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ACE9030  
ABSOLUTE MAXIMUM RATINGS  
tions VDDSUB and VDDSUB2 must be the most positive of all VDD’s  
at all times including during power on and off ramping. As the  
current taken through these VDD’s is significantly less than  
through the other VDD’s this requirement can be easily met by  
directly connecting all VDD pins to a common point on the  
circuit board but with the decoupling capacitors distributed to  
minimise cross-talk caused by common mode currents. If low  
value series resistors are to be included in the VDD connec-  
tions, with decoupling capacitors by the ACE9030 pins to  
further reduce interference, the VDDSUB and VDDSUB2 pins should  
not have such a resistor in order to guarantee that their  
voltage is not slowed down at power-on. Power switches to  
DOUT0 and DOUT1 are supplied from VDDX and are specified  
for a total current of up to 40 mA so any resistor in the VDDX  
connection must be very low, around 1, in order to avoid  
excessive voltage drop; it is recommended that this supply  
hasnoseriesresistor. Thesetwomethodsareshownincircuit  
diagrams, figures 4 and 5. In both circuits the main VDD must  
also have good decoupling.  
Supply voltage from ground  
(any VDD to any VSS)  
Supply voltage difference  
– 0·3 V to + 6·0 V  
– 0·3 V to + 0·3 V  
(any VDD to any other VDD)  
Input voltage  
VSS – 0·3 V to VDD + 0·3 V  
(any input pin to its local VSS and VDD)  
Output voltage  
VSS – 0·3 V to VDD + 0·3 V  
(any output pin to its local VSS and VDD)  
Storage temperature  
Operating temperature  
– 55 °C to + 150 °C  
– 40 °C to + 85 °C  
These are not the operating conditions, but are the  
absolute limits which if exceeded even momentarily may  
cause permanent damage. To ensure sustained correct op-  
eration the device should be used within the limits given under  
Electrical Characteristics.  
To avoid any possibility of latch-up the substrate connec-  
Main VDD  
VDDSUB  
VDDSUB2  
VDDL  
VDDA  
VDDX  
VDDD  
VDDSA  
Fig.4 Typical VDD local decoupling networks without series resistors  
Main VDD  
Very  
Small  
No Resistor  
VDDSUB  
No Resistor  
VDDSUB2  
VDDL  
VDDA  
VDDX  
VDDD  
VDDSA  
Fig.5 Typical VDD local decoupling networks with series resistors  
4