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ACE9030MIWFP2Q 参数 Datasheet PDF下载

ACE9030MIWFP2Q图片预览
型号: ACE9030MIWFP2Q
PDF下载: 下载PDF文件 查看货源
内容描述: 无线接口和双合成器 [Radio Interface and Twin Synthesiser]
分类和应用: 无线
文件页数/大小: 39 页 / 382 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ACE9030  
ELECTRICAL CHARACTERISTICS  
These characteristics apply over these ranges of conditions (unless otherwise stated):  
TAMB = – 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = VSS  
D.C. Characteristics  
Parameter  
Min.  
Typ.  
Max.  
Unit Conditions  
Power supply  
Supply current, Radio Interface:  
Sleep mode  
2.3  
2·7  
7
mA XO, OSC8 on  
mA (see Note 1)  
fREF = 10 MHz  
Fully operating (excluding IDDX  
)
Supply current, Synthesisers: VDD=5V  
Main and Auxiliary ON  
Main ON and Auxiliary in Standby  
Main in Standby and Auxiliary ON  
Main and Auxiliary in Standby, with Bandgap off  
Supply current, Synthesisers:  
5
3.7  
3
mA  
fMAIN = 10 MHz  
mA fAUX = 10 MHz  
mA (see Note 2)  
µA  
100  
fREF = 15 MHz  
Main and Auxiliary ON  
3
2
2
mA  
fMAIN = 16 MHz  
Main ON and Auxiliary in Standby  
Main in Standby and Auxiliary ON  
Main and Auxiliary in Standby  
mA fAUX = 90 MHz  
mA (see Note 2)  
µA  
100  
Input and output signals  
Logic input HIGH (LATCHC, LATCHB, DATA,  
CL, and TEST)  
Logic input LOW (LATCHC, LATCHB, DATA,  
CL, and TEST)  
Input capacitance (signal pins)  
Input leakage (signal pins)  
Logic output HIGH (RXCD, DATA, AFCOUT,  
TEST and DOUT2, 3 and 4)  
0·7 x VDD  
– 0·3  
VDD + 0·3  
V
+ 0·8  
10  
1
V
pF Pin voltage  
µA VSS to VDD  
V
VDD – 0·5  
External load:  
Logic output LOW (RXCD, DATA, AFCOUT,  
TEST and DOUT2, 3 and 4)  
0·4  
V
20 k& 30 pF  
Output ON level, DOUT0 and DOUT1  
Output HIGH level, DOUT5, 6 and 7  
Output LOW level, DOUT5, 6 and 7  
Trimmed output level ON, DOUT8  
Level difference, DOUT8 ON – ADC reference  
Output level OFF, DOUT8  
VDDX – 0·2  
2·3  
V
V
V
V
mV  
V
IOH = 20 mA.  
IOH = 80 µA  
IOL = 0.2 µA  
IOH = 135 to 400 µA.  
2·9  
0·3  
3·55  
+ 15  
0.4  
3·35  
– 5  
MODMP, MODMN output HIGH  
MODMP, MODMN output LOW  
Input Schmitt Hysteresis, pins CL, LATCHB,  
LATCHC, DATA.  
VDD/2 + 0·35  
VDD/2 – 1·0  
0·3  
VDD/2 + 1·0  
VDD/2 – 0·35  
V
V
V
IOH = 10 µA  
IOL = – 10 µA  
Analog circuits bias resistor on IREF  
68  
100  
kVDD @ 3·75 V  
kDD @ 4·85 V  
V
Notes  
1. Thesleepcurrentisspecifiedwiththecrystaloscillator(XO)andtheOSC8oscillatorandPLLrunningasthesearenormallyneededtoprovide  
the clock to the system controller.  
2. The terms fREF, fMAIN, and fAUX refer to the frequencies of the Reference inputs (Crystal oscillator, pins CIN1 and CIN2), the Main synthesiser  
inputs (pins FIM and FIMB) and the Auxiliary synthesiser inputs (pins FIA and FIAB) respectively.  
5