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ACE9030MIWFP2Q 参数 Datasheet PDF下载

ACE9030MIWFP2Q图片预览
型号: ACE9030MIWFP2Q
PDF下载: 下载PDF文件 查看货源
内容描述: 无线接口和双合成器 [Radio Interface and Twin Synthesiser]
分类和应用: 无线
文件页数/大小: 39 页 / 382 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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ACE9030  
ELECTRICAL CHARACTERISTICS  
These characteristics apply over these ranges of conditions (unless otherwise stated):  
TAMB = – 40 °C to + 85 °C, all VDD = + 3·6 to + 5·0 V, GND ref. = VSS  
A.C. Characteristics (continued)  
Parameter  
Min.  
Typ.  
Max.  
Unit Conditions  
LO2 Multiplier  
Amplitude  
235  
500  
-10.5  
-13.5  
-15  
mVrms Circuit as in fig. 15,  
Reference frequency content of output  
2nd, 4th harmonic content of output  
5th harmonic of output  
6th and higher harmonics in output  
SYNTHESISERS  
dBc  
dBc  
dBc  
dBc  
-20  
Reference divider  
Reference divider input frequency  
Drive level into CIN1 from external oscillator  
5
400  
30  
10  
MHz  
mVpk-pk With crystal oscillator  
powered down  
CIN1 input capacitance  
CIN1 input resistance  
Auxiliary synthesiser  
FIA input frequency  
Rise and fall times of inputs  
Timing Skew between FIA and FIAB  
pF  
kΩ  
10  
10  
135  
10  
± 2  
MHz May be a sinewave  
ns  
ns See Fig. 6  
or ± 10%  
signal Both maxima  
period must be met  
mVpk-pk Each input, 5 to 50 &  
99 to 135 MHz  
FIA, FIAB differential signal level with both  
sides driven  
180  
100  
360  
200  
mV pk-pk Each input,  
50 to 99 MHz  
mVpk-pk One input, 5 to 50 &  
99 to 135 MHz  
mVpk-pk One input,  
50 to 99 MHz  
FIA single input drive level with FIAB  
decoupled to VSS  
FIA, FIAB common mode range  
FIA, FIAB common mode range  
FIA, FIAB input capacitance  
FIA, FIAB differential input resistance  
Auxiliary Synthesiser comparison frequency  
Main Synthesiser  
FIM input frequency  
Rise and fall times of inputs  
FIM - FIMB Timing Skew  
VDD – 1·7  
2.8  
VDD – 0·7  
VDD – 0·85  
10  
V
V
pF  
VDD = 3.6V  
VDD = 5V  
10  
4
kNote 8  
MHz  
2
20  
50  
± 2  
MHz  
ns  
ns See Fig. 6  
signal Both maxima  
period must be met  
mVpk-pk Each input,  
4 to 20 MHz  
or ± 10%  
FIM, FIMB differential signal level  
with both sides driven.  
FIM single input drive level  
100  
200  
1000  
mVpk-pk One input,  
4 to 20 MHz  
with FIMB decoupled to VSS  
FIM, FIMB common mode range  
FIM, FIMB common mode range  
FIM, FIMB input capacitance  
VDD – 1·7  
2·8  
VDD – 0·7  
VDD – 0·85  
10  
V
V
pF  
VDD =3.6V  
VDD =5V  
FIM, FIMB differential input resistance  
Delay FIM rising to MODMP/MODMN changing  
Main Synthesiser comparison frequency  
10  
kNote 8  
ns  
MHz  
30  
2
Note  
8. To simplify single ended drive there is a resistor between FIA and FIAB and another between FIM and FIMB. In this mode the inputs should  
drive FIA or FIM with D.C. coupling and the other inputs FIAB and FIMB should be decoupled to ground by external capacitors.  
9